325 lines
11 KiB
Rust
325 lines
11 KiB
Rust
use paste::paste;
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use crate::{
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gpio::PhantomData,
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peripherals::GPIO,
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AlternateFunction,
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Bank0GpioRegisterAccess,
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Bank1GpioRegisterAccess,
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GpioPin,
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InputOutputAnalogPinType,
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InputOutputPinType,
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Unknown,
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};
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pub type OutputSignalType = u16;
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pub const OUTPUT_SIGNAL_MAX: u16 = 256;
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pub const INPUT_SIGNAL_MAX: u16 = 189;
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pub const ONE_INPUT: u8 = 0x38;
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pub const ZERO_INPUT: u8 = 0x3c;
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pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
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pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
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unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio[gpio_num as usize] }
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}
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pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
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int_enable as u8 | ((nmi_enable as u8) << 1)
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}
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/// Peripheral input signals for the GPIO mux
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#[allow(non_camel_case_types)]
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#[derive(PartialEq, Copy, Clone)]
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pub enum InputSignal {
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SPIQ = 0,
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SPID = 1,
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SPIHD = 2,
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SPIWP = 3,
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SPID4 = 7,
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SPID5 = 8,
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SPID6 = 9,
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SPID7 = 10,
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SPIDQS = 11,
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U0RXD = 12,
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U0CTS = 13,
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U0DSR = 14,
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U1RXD = 15,
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U1CTS = 16,
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U1DSR = 17,
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U2RXD = 18,
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U2CTS = 19,
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U2DSR = 20,
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I2S1_MCLK = 21,
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I2S0O_BCK = 22,
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I2S0_MCLK = 23,
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I2S0O_WS = 24,
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I2S0I_SD = 25,
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I2S0I_BCK = 26,
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I2S0I_WS = 27,
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I2S1O_BCK = 28,
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I2S1O_WS = 29,
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I2S1I_SD = 30,
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I2S1I_BCK = 31,
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I2S1I_WS = 32,
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I2S0I_SD1 = 51,
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I2S0I_SD2 = 52,
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I2S0I_SD3 = 53,
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USB_OTG_IDDIG = 58,
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USB_OTG_AVALID = 59,
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USB_SRP_BVALID = 60,
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USB_OTG_VBUSVALID = 61,
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USB_SRP_SESSEND = 62,
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SPI3_CLK = 66,
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SPI3_Q = 67,
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SPI3_D = 68,
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SPI3_HD = 69,
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SPI3_WP = 70,
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SPI3_CS0 = 71,
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RMT_SIG_IN0 = 81,
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RMT_SIG_IN1 = 82,
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RMT_SIG_IN2 = 83,
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RMT_SIG_IN3 = 84,
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I2CEXT0_SCL = 89,
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I2CEXT0_SDA = 90,
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I2CEXT1_SCL = 91,
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I2CEXT1_SDA = 92,
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FSPICLK = 101,
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FSPIQ = 102,
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FSPID = 103,
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FSPIHD = 104,
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FSPIWP = 105,
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FSPIIO4 = 106,
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FSPIIO5 = 107,
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FSPIIO6 = 108,
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FSPIIO7 = 109,
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FSPICS0 = 110,
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TWAI_RX = 116,
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SUBSPIQ = 120,
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SUBSPID = 121,
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SUBSPIHD = 122,
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SUBSPIWP = 123,
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SUBSPID4 = 155,
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SUBSPID5 = 156,
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SUBSPID6 = 157,
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SUBSPID7 = 158,
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SUBSPIDQS = 159,
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PWM0_SYNC0 = 160,
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PWM0_SYNC1 = 161,
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PWM0_SYNC2 = 162,
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PWM0_F0 = 163,
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PWM0_F1 = 164,
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PWM0_F2 = 165,
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PWM0_CAP0 = 166,
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PWM0_CAP1 = 167,
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PWM0_CAP2 = 168,
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PWM1_SYNC0 = 169,
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PWM1_SYNC1 = 170,
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PWM1_SYNC2 = 171,
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PWM1_F0 = 172,
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PWM1_F1 = 173,
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PWM1_F2 = 174,
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PWM1_CAP0 = 175,
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PWM1_CAP1 = 176,
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PWM1_CAP2 = 177,
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PCMFSYNC = 188,
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PCMCLK = 189,
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}
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/// Peripheral output signals for the GPIO mux
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#[allow(non_camel_case_types)]
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#[derive(PartialEq, Copy, Clone)]
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pub enum OutputSignal {
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SPIQ = 0,
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SPID = 1,
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SPIHD = 2,
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SPIWP = 3,
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SPICLK = 4,
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SPICS0 = 5,
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SPICS1 = 6,
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SPID4 = 7,
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SPID5 = 8,
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SPID6 = 9,
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SPID7 = 10,
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SPIDQS = 11,
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U0TXD = 12,
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U0RTS = 13,
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U0DTR = 14,
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U1TXD = 15,
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U1RTS = 16,
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U1DTR = 17,
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U2TXD = 18,
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U2RTS = 19,
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U2DTR = 20,
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I2S1_MCLK = 21,
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I2S0O_BCK = 22,
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I2S0_MCLK = 23,
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I2S0O_WS = 24,
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I2S0O_SD = 25,
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I2S0I_BCK = 26,
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I2S0I_WS = 27,
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I2S1O_BCK = 28,
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I2S1O_WS = 29,
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I2S1O_SD = 30,
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I2S1I_BCK = 31,
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I2S1I_WS = 32,
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SPI3_CLK = 66,
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SPI3_Q = 67,
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SPI3_D = 68,
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SPI3_HD = 69,
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SPI3_WP = 70,
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SPI3_CS0 = 71,
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SPI3_CS1 = 72,
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LEDC_LS_SIG0 = 73,
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LEDC_LS_SIG1 = 74,
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LEDC_LS_SIG2 = 75,
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LEDC_LS_SIG3 = 76,
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LEDC_LS_SIG4 = 77,
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LEDC_LS_SIG5 = 78,
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LEDC_LS_SIG6 = 79,
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LEDC_LS_SIG7 = 80,
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RMT_SIG_OUT0 = 81,
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RMT_SIG_OUT1 = 82,
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RMT_SIG_OUT2 = 83,
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RMT_SIG_OUT3 = 84,
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I2CEXT0_SCL = 89,
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I2CEXT0_SDA = 90,
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I2CEXT1_SCL = 91,
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I2CEXT1_SDA = 92,
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GPIO_SD0 = 93,
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GPIO_SD1 = 94,
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GPIO_SD2 = 95,
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GPIO_SD3 = 96,
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GPIO_SD4 = 97,
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GPIO_SD5 = 98,
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GPIO_SD6 = 99,
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GPIO_SD7 = 100,
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FSPICLK = 101,
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FSPIQ = 102,
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FSPID = 103,
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FSPIHD = 104,
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FSPIWP = 105,
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FSPIIO4 = 106,
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FSPIIO5 = 107,
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FSPIIO6 = 108,
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FSPIIO7 = 109,
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FSPICS0 = 110,
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FSPICS1 = 111,
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FSPICS2 = 112,
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FSPICS3 = 113,
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FSPICS4 = 114,
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FSPICS5 = 115,
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TWAI_TX = 116,
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SUBSPICLK = 119,
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SUBSPIQ = 120,
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SUBSPID = 121,
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SUBSPIHD = 122,
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SUBSPIWP = 123,
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SUBSPICS0 = 124,
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SUBSPICS1 = 125,
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FSPIDQS = 126,
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SPI3_CS2 = 127,
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I2S0O_SD1 = 128,
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SUBSPID4 = 155,
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SUBSPID5 = 156,
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SUBSPID6 = 157,
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SUBSPID7 = 158,
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SUBSPIDQS = 159,
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PWM0_0A = 160,
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PWM0_0B = 161,
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PWM0_1A = 162,
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PWM0_1B = 163,
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PWM0_2A = 164,
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PWM0_2B = 165,
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PWM1_0A = 166,
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PWM1_0B = 167,
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PWM1_1A = 168,
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PWM1_1B = 169,
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PWM1_2A = 170,
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PWM1_2B = 171,
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SDIO_TOHOST_INT = 177,
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PCMFSYNC = 194,
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PCMCLK = 195,
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GPIO = 256,
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}
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crate::gpio::gpio! {
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Single,
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(0, 0, InputOutputAnalog)
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(1, 0, InputOutputAnalog)
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(2, 0, InputOutputAnalog)
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(3, 0, InputOutputAnalog)
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(4, 0, InputOutputAnalog)
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(5, 0, InputOutputAnalog)
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(6, 0, InputOutputAnalog)
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(7, 0, InputOutputAnalog)
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(8, 0, InputOutputAnalog () (3 => SUBSPICS1))
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(9, 0, InputOutputAnalog (3 => SUBSPIHD 4 => FSPIHD) (3 => SUBSPIHD 4 => FSPIHD))
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(10, 0, InputOutputAnalog (2 => FSPIIO4 4 => FSPICS0) (2 => FSPIIO4 3 => SUBSPICS0 4 => FSPICS0))
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(11, 0, InputOutputAnalog (2 => FSPIIO5 3 => SUBSPID 4 => FSPID) (2 => FSPIIO5 3 => SUBSPID 4 => FSPID))
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(12, 0, InputOutputAnalog (2 => FSPIIO6 4 => FSPICLK) (2 => FSPIIO6 3=> SUBSPICLK 4 => FSPICLK))
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(13, 0, InputOutputAnalog (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ) (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ))
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(14, 0, InputOutputAnalog (3 => SUBSPIWP 4 => FSPIWP) (2 => FSPIDQS 3 => SUBSPIWP 4 => FSPIWP))
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(15, 0, InputOutputAnalog () (2 => U0RTS))
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(16, 0, InputOutputAnalog (2 => U0CTS) ())
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(17, 0, InputOutputAnalog () (2 => U1TXD))
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(18, 0, InputOutputAnalog (2 => U1RXD) ())
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(19, 0, InputOutputAnalog () (2 => U1RTS))
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(20, 0, InputOutputAnalog (2 => U1CTS) ())
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(21, 0, InputOutputAnalog)
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(26, 0, InputOutput)
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(27, 0, InputOutput)
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(28, 0, InputOutput)
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(29, 0, InputOutput)
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(30, 0, InputOutput)
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(31, 0, InputOutput)
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(32, 1, InputOutput)
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(33, 1, InputOutput (2 => FSPIHD 3 => SUBSPIHD) (2 => FSPIHD 3 => SUBSPIHD))
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(34, 1, InputOutput (2 => FSPICS0) (2 => FSPICS0 3 => SUBSPICS0))
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(35, 1, InputOutput (2 => FSPID 3 => SUBSPID) (2 => FSPID 3 => SUBSPID))
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(36, 1, InputOutput (2 => FSPICLK) (2 => FSPICLK 3 => SUBSPICLK))
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(37, 1, InputOutput (2 => FSPIQ 3 => SUBSPIQ 4 => SPIDQS) (2 => FSPIQ 3=> SUBSPIQ 4 => SPIDQS))
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(38, 1, InputOutput (2 => FSPIWP 3 => SUBSPIWP) (3 => FSPIWP 3 => SUBSPIWP))
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(39, 1, InputOutput () (4 => SUBSPICS1))
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(40, 1, InputOutput)
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(41, 1, InputOutput)
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(42, 1, InputOutput)
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(43, 1, InputOutput)
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(44, 1, InputOutput)
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(45, 1, InputOutput)
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(46, 1, InputOutput)
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(47, 1, InputOutput)
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(48, 1, InputOutput)
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}
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crate::gpio::analog! {
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( 0, 0, touch_pad0, mux_sel, fun_sel, fun_ie, rue, rde)
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( 1, 1, touch_pad1, mux_sel, fun_sel, fun_ie, rue, rde)
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( 2, 2, touch_pad2, mux_sel, fun_sel, fun_ie, rue, rde)
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( 3, 3, touch_pad3, mux_sel, fun_sel, fun_ie, rue, rde)
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( 4, 4, touch_pad4, mux_sel, fun_sel, fun_ie, rue, rde)
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( 5, 5, touch_pad5, mux_sel, fun_sel, fun_ie, rue, rde)
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( 6, 6, touch_pad6, mux_sel, fun_sel, fun_ie, rue, rde)
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( 7, 7, touch_pad7, mux_sel, fun_sel, fun_ie, rue, rde)
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( 8, 8, touch_pad8, mux_sel, fun_sel, fun_ie, rue, rde)
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( 9, 9, touch_pad9, mux_sel, fun_sel, fun_ie, rue, rde)
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(10, 10, touch_pad10, mux_sel, fun_sel, fun_ie, rue, rde)
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(11, 11, touch_pad11, mux_sel, fun_sel, fun_ie, rue, rde)
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(12, 12, touch_pad12, mux_sel, fun_sel, fun_ie, rue, rde)
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(13, 13, touch_pad13, mux_sel, fun_sel, fun_ie, rue, rde)
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(14, 14, touch_pad14, mux_sel, fun_sel, fun_ie, rue, rde)
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(15, 15, xtal_32p_pad, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_rue, x32p_rde)
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(16, 16, xtal_32n_pad, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_rue, x32n_rde)
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(17, 17, pad_dac1, pdac1_mux_sel,pdac1_fun_sel,pdac1_fun_ie, pdac1_rue, pdac1_rde)
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(18, 18, pad_dac2, pdac2_mux_sel,pdac2_fun_sel,pdac2_fun_ie, pdac2_rue, pdac2_rde)
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(19, 19, rtc_pad19, mux_sel, fun_sel, fun_ie, rue, rde)
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(20, 20, rtc_pad20, mux_sel, fun_sel, fun_ie, rue, rde)
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(21, 21, rtc_pad21, mux_sel, fun_sel, fun_ie, rue, rde)
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}
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// implement marker traits on USB pins
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impl<T> crate::otg_fs::UsbSel for Gpio18<T> {}
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impl<T> crate::otg_fs::UsbDp for Gpio19<T> {}
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impl<T> crate::otg_fs::UsbDm for Gpio20<T> {}
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