198 lines
5.3 KiB
Rust
198 lines
5.3 KiB
Rust
use paste::paste;
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use crate::{
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gpio::PhantomData,
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peripherals::GPIO,
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AlternateFunction,
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Bank0GpioRegisterAccess,
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GpioPin,
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InputOutputAnalogPinType,
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InputOutputPinType,
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Unknown,
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};
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pub type OutputSignalType = u8;
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pub const OUTPUT_SIGNAL_MAX: u8 = 128;
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pub const INPUT_SIGNAL_MAX: u8 = 100;
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pub const ONE_INPUT: u8 = 0x1e;
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pub const ZERO_INPUT: u8 = 0x1f;
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pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
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pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
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unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio[gpio_num as usize] }
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}
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pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
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int_enable as u8 | ((nmi_enable as u8) << 1)
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}
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/// Peripheral input signals for the GPIO mux
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#[allow(non_camel_case_types)]
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#[derive(Clone, Copy, PartialEq)]
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pub enum InputSignal {
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SPIQ = 0,
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SPID = 1,
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SPIHD = 2,
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SPIWP = 3,
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U0RXD = 6,
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U0CTS = 7,
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U0DSR = 8,
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U1RXD = 9,
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U1CTS = 10,
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U1DSR = 11,
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I2S_MCLK = 12,
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I2SO_BCK = 13,
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I2SO_WS = 14,
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I2SI_SD = 15,
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I2SI_BCK = 16,
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I2SI_WS = 17,
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GPIO_BT_PRIORITY = 18,
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GPIO_BT_ACTIVE = 19,
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CPU_GPIO_0 = 28,
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CPU_GPIO_1 = 29,
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CPU_GPIO_2 = 30,
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CPU_GPIO_3 = 31,
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CPU_GPIO_4 = 32,
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CPU_GPIO_5 = 33,
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CPU_GPIO_6 = 34,
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CPU_GPIO_7 = 35,
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EXT_ADC_START = 45,
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RMT_SIG_0 = 51,
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RMT_SIG_1 = 52,
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I2CEXT0_SCL = 53,
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I2CEXT0_SDA = 54,
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FSPICLK = 63,
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FSPIQ = 64,
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FSPID = 65,
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FSPIHD = 66,
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FSPIWP = 67,
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FSPICS0 = 68,
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TWAI_RX = 74,
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SIG_FUNC_97 = 97,
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SIG_FUNC_98 = 98,
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SIG_FUNC_99 = 99,
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SIG_FUNC_100 = 100,
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}
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/// Peripheral output signals for the GPIO mux
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#[allow(non_camel_case_types)]
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#[derive(Clone, Copy, PartialEq)]
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pub enum OutputSignal {
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SPIQ = 0,
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SPID = 1,
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SPIHD = 2,
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SPIWP = 3,
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SPICLK_MUX = 4,
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SPICS0 = 5,
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U0TXD = 6,
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U0RTS = 7,
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U0DTR = 8,
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U1TXD = 9,
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U1RTS = 10,
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U1DTR = 11,
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I2S_MCLK = 12,
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I2SO_BCK = 13,
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I2SO_WS = 14,
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I2SI_SD = 15,
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I2SI_BCK = 16,
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I2SI_WS = 17,
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GPIO_WLAN_PRIO = 18,
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GPIO_WLAN_ACTIVE = 19,
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CPU_GPIO_0 = 28,
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CPU_GPIO_1 = 29,
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CPU_GPIO_2 = 30,
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CPU_GPIO_3 = 31,
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CPU_GPIO_4 = 32,
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CPU_GPIO_5 = 33,
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CPU_GPIO_6 = 34,
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CPU_GPIO_7 = 35,
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USB_JTAG_TCK = 36,
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USB_JTAG_TMS = 37,
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USB_JTAG_TDI = 38,
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USB_JTAG_TDO = 39,
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LEDC_LS_SIG0 = 45,
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LEDC_LS_SIG1 = 46,
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LEDC_LS_SIG2 = 47,
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LEDC_LS_SIG3 = 48,
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LEDC_LS_SIG4 = 49,
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LEDC_LS_SIG5 = 50,
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RMT_SIG_0 = 51,
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RMT_SIG_1 = 52,
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I2CEXT0_SCL = 53,
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I2CEXT0_SDA = 54,
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GPIO_SD0 = 55,
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GPIO_SD1 = 56,
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GPIO_SD2 = 57,
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GPIO_SD3 = 58,
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I2SO_SD1 = 59,
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FSPICLK_MUX = 63,
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FSPIQ = 64,
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FSPID = 65,
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FSPIHD = 66,
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FSPIWP = 67,
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FSPICS0 = 68,
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FSPICS1 = 69,
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FSPICS3 = 70,
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FSPICS2 = 71,
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FSPICS4 = 72,
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FSPICS5 = 73,
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TWAI_TX = 74,
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TWAI_BUS_OFF_ON = 75,
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TWAI_CLKOUT = 76,
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ANT_SEL0 = 89,
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ANT_SEL1 = 90,
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ANT_SEL2 = 91,
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ANT_SEL3 = 92,
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ANT_SEL4 = 93,
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ANT_SEL5 = 94,
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ANT_SEL6 = 95,
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ANT_SEL7 = 96,
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SIG_FUNC_97 = 97,
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SIG_FUNC_98 = 98,
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SIG_FUNC_99 = 99,
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SIG_FUNC_100 = 100,
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CLK_OUT1 = 123,
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CLK_OUT2 = 124,
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CLK_OUT3 = 125,
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SPICS1 = 126,
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USB_JTAG_TRST = 127,
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GPIO = 128,
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}
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crate::gpio::gpio! {
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Single,
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(0, 0, InputOutputAnalog)
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(1, 0, InputOutputAnalog)
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(2, 0, InputOutputAnalog (2 => FSPIQ) (2 => FSPIQ))
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(3, 0, InputOutputAnalog)
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(4, 0, InputOutputAnalog (2 => FSPIHD) (0 => USB_JTAG_TMS 2 => FSPIHD))
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(5, 0, InputOutputAnalog (2 => FSPIWP) (0 => USB_JTAG_TDI 2 => FSPIWP))
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(6, 0, InputOutput (2 => FSPICLK) (0 => USB_JTAG_TCK 2 => FSPICLK_MUX))
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(7, 0, InputOutput (2 => FSPID) (0 => USB_JTAG_TDO 2 => FSPID))
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(8, 0, InputOutput)
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(9, 0, InputOutput)
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(10, 0, InputOutput (2 => FSPICS0) (2 => FSPICS0))
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(11, 0, InputOutput)
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(12, 0, InputOutput (0 => SPIHD) (0 => SPIHD))
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(13, 0, InputOutput (0 => SPIWP) (0 => SPIWP))
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(14, 0, InputOutput () (0 => SPICS0))
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(15, 0, InputOutput () (0 => SPICLK_MUX))
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(16, 0, InputOutput (0 => SPID) (0 => SPID))
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(17, 0, InputOutput (0 => SPIQ) (0 => SPIQ))
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(18, 0, InputOutput)
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(19, 0, InputOutput)
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(20, 0, InputOutput (0 => U0RXD) ())
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(21, 0, InputOutput () (0 => U0TXD))
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}
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crate::gpio::analog! {
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0
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1
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2
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3
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4
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5
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}
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