9bf70ff792
* Combine `esp-ulp-riscv-hal` and `esp32c6-lp-hal` into a single package * Update LP core examples * Update CI workflow * Fix `LP_UART` example
151 lines
3.0 KiB
Rust
151 lines
3.0 KiB
Rust
#![allow(asm_sub_register)]
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#![no_std]
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use core::arch::global_asm;
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pub mod delay;
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pub mod gpio;
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#[cfg(esp32c6)]
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pub mod uart;
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pub mod pac {
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#[cfg(feature = "esp32c6")]
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pub use esp32c6_lp::*;
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#[cfg(feature = "esp32s2")]
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pub use esp32s2_ulp::*;
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#[cfg(feature = "esp32s3")]
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pub use esp32s3_ulp::*;
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}
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pub mod prelude {
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pub use procmacros::entry;
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}
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cfg_if::cfg_if! {
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if #[cfg(feature = "esp32c6")] {
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// LP_FAST_CLK is not very accurate, for now use a rough estimate
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const LP_FAST_CLK_HZ: u32 = 16_000_000;
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const XTAL_D2_CLK_HZ: u32 = 20_000_000;
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} else if #[cfg(feature = "esp32s2")] {
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const LP_FAST_CLK_HZ: u32 = 8_000_000;
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} else if #[cfg(feature = "esp32s3")] {
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const LP_FAST_CLK_HZ: u32 = 17_500_000;
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}
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}
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pub static mut CPU_CLOCK: u32 = LP_FAST_CLK_HZ;
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#[cfg(feature = "esp32c6")]
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global_asm!(
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r#"
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.section .init.vector, "ax"
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/* This is the vector table. It is currently empty, but will be populated
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* with exception and interrupt handlers when this is supported
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*/
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.align 0x4, 0xff
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.global _vector_table
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.type _vector_table, @function
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_vector_table:
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.option push
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.option norvc
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.rept 32
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nop
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.endr
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.option pop
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.size _vector_table, .-_vector_table
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.section .init, "ax"
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.global reset_vector
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/* The reset vector, jumps to startup code */
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reset_vector:
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j __start
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__start:
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/* setup the stack pointer */
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la sp, __stack_top
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call rust_main
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loop:
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j loop
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"#
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);
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#[cfg(any(feature = "esp32s2", feature = "esp32s3"))]
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global_asm!(
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r#"
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.section .text.vectors
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.global irq_vector
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.global reset_vector
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/* The reset vector, jumps to startup code */
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reset_vector:
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j __start
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/* Interrupt handler */
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.balign 16
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irq_vector:
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ret
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.section .text
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__start:
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/* setup the stack pointer */
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la sp, __stack_top
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call ulp_riscv_rescue_from_monitor
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call rust_main
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call ulp_riscv_halt
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loop:
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j loop
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"#
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);
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#[link_section = ".init.rust"]
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#[export_name = "rust_main"]
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unsafe extern "C" fn lp_core_startup() -> ! {
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extern "Rust" {
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fn main() -> !;
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}
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#[cfg(feature = "esp32c6")]
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if (*pac::LP_CLKRST::PTR)
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.lp_clk_conf()
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.read()
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.fast_clk_sel()
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.bit_is_set()
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{
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CPU_CLOCK = XTAL_D2_CLK_HZ;
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}
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main();
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}
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#[cfg(any(feature = "esp32s2", feature = "esp32s3"))]
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#[link_section = ".init.rust"]
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#[no_mangle]
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unsafe extern "C" fn ulp_riscv_rescue_from_monitor() {
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// Rescue RISC-V core from monitor state.
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unsafe { &*pac::RTC_CNTL::PTR }
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.cocpu_ctrl()
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.modify(|_, w| w.cocpu_done().clear_bit().cocpu_shut_reset_en().clear_bit());
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}
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#[cfg(any(feature = "esp32s2", feature = "esp32s3"))]
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#[link_section = ".init.rust"]
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#[no_mangle]
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unsafe extern "C" fn ulp_riscv_halt() {
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unsafe { &*pac::RTC_CNTL::PTR }.cocpu_ctrl().modify(|_, w| {
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w.cocpu_shut_2_clk_dis()
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.variant(0x3f)
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.cocpu_done()
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.set_bit()
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});
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loop {
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riscv::asm::wfi();
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}
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}
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