* removed eh02 dependencies, sh*tcode, not yet tested properly,copy-pasted * changelog entry * Don't implement eh1 traits
84 lines
2.1 KiB
Rust
84 lines
2.1 KiB
Rust
//! # Delay driver
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//!
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//! ## Overview
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//!
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//! The delay driver provides blocking delay functionality. The driver
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//! implements the relevant traits from `embedded-hal`.
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//!
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//! ## Examples
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//!
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//! ```rust
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//! esp_lp_hal::delay::Delay.delay_millis(500);
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//! ```
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/// Delay driver
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#[derive(Debug, Clone, Copy)]
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pub struct Delay;
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impl Delay {
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/// Delay for at least the number of specific milliseconds.
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pub fn delay_millis(&self, mut ms: u32) {
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const MICROS_PER_MILLI: u32 = 1_000;
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const MAX_MILLIS: u32 = u32::MAX / MICROS_PER_MILLI;
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// Avoid potential overflow if milli -> micro conversion is too large
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while ms > MAX_MILLIS {
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ms -= MAX_MILLIS;
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self.delay_micros(MAX_MILLIS * MICROS_PER_MILLI);
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}
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self.delay_micros(ms * MICROS_PER_MILLI);
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}
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/// Delay for at least the number of specific microseconds.
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pub fn delay_micros(&self, mut us: u32) {
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const NANOS_PER_MICRO: u32 = 1_000;
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const MAX_MICROS: u32 = u32::MAX / NANOS_PER_MICRO;
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// Avoid potential overflow if micro -> nano conversion is too large
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while us > MAX_MICROS {
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us -= MAX_MICROS;
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self.delay_nanos(MAX_MICROS * NANOS_PER_MICRO);
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}
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self.delay_nanos(us * NANOS_PER_MICRO);
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}
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/// Delay for at least the number of specific nanoseconds.
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pub fn delay_nanos(&self, ns: u32) {
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let ticks_seconds = unsafe { crate::CPU_CLOCK };
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let clock = (ns as u64 * (ticks_seconds as u64)) / 1_000_000_000u64;
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let t0 = cycles();
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while cycles().wrapping_sub(t0) <= clock {}
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}
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}
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#[cfg(feature = "esp32c6")]
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#[inline(always)]
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fn cycles() -> u64 {
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riscv::register::mcycle::read64()
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}
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#[cfg(any(feature = "esp32s2", feature = "esp32s3"))]
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#[inline(always)]
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fn cycles() -> u64 {
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let mut cycles: u32;
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unsafe {
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core::arch::asm!(
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"rdcycle {cycles}",
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cycles = out(reg) cycles,
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)
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}
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cycles as u64
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}
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#[cfg(feature = "embedded-hal")]
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impl embedded_hal::delay::DelayNs for Delay {
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#[inline(always)]
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fn delay_ns(&mut self, ns: u32) {
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self.delay_nanos(ns);
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}
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}
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