9a5a546228
* esp32 & esp32s2 sharing scripts * add wokwi files * Add fixup section for esp32s2, fix ordering of sectino includes * Remove debug asm file * Use shared linker scripts for s3 with fixups * Add external.x sections back * Move ld scripts into esp-hal-common * esp32c3 unified linker scripts - rework original c3 script to use the xtensa named sections (e.g, _SECTIONNAME_start) - Add fixups in esp32c3 specific linker - Remove useless text section start and end (not required when using any form of bootloader) * Add RTC alias'. Move some shared fixups to a file * comment and cleanup * unify c2 linker script * unify c6 linker script * remove debug configs * use new esp-riscv-rt * fmt * align db symbol names * fix s3 db
61 lines
2.5 KiB
Plaintext
61 lines
2.5 KiB
Plaintext
/* This memory map assumes the flash cache is on;
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the blocks used are excluded from the various memory ranges
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see: https://github.com/espressif/esp-idf/blob/5b1189570025ba027f2ff6c2d91f6ffff3809cc2/components/heap/port/esp32s2/memory_layout.c
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for details
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*/
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/* override entry point */
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ENTRY(ESP32Reset)
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/* reserved at the start of DRAM/IRAM */
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RESERVE_CACHES = 0x2000;
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VECTORS_SIZE = 0x400;
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/* reserved at the start of the RTC memories for use by the ULP processor */
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RESERVE_RTC_FAST = 0;
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RESERVE_RTC_SLOW = 0;
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/* define stack size for both cores */
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STACK_SIZE = 8k;
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/* Specify main memory areas */
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MEMORY
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{
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vectors_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES, len = VECTORS_SIZE /* SRAM0 */
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iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES + VECTORS_SIZE, len = 192k - RESERVE_CACHES - VECTORS_SIZE /* SRAM0 */
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dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_CACHES + VECTORS_SIZE, len = 192k - RESERVE_CACHES - VECTORS_SIZE
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/* SRAM1; reserved for static ROM usage; can be used for heap.
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Length based on the "_dram0_rtos_reserved_start" symbol from IDF used to delimit the
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ROM data reserved region:
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https://github.com/espressif/esp-idf/blob/bcb34ca7aef4e8d3b97d75ad069b960fb1c17c16/components/heap/port/esp32s2/memory_layout.c#L121-L122
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*/
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reserved_for_boot_seg : ORIGIN = 0x3FFE0000, len = 0x1FA10
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/* external flash
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The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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irom_seg ( RX ) : ORIGIN = 0x40080020, len = 3M - 0x20
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drom_seg ( R ) : ORIGIN = 0x3F000020, len = 4M - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
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rtc_fast_iram_seg(RWX) : ORIGIN = 0x40070000, len = 8k
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/* RTC fast memory (same block as above), viewed from data bus. Only for core 0 (PRO_CPU) */
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rtc_fast_dram_seg(RW) : ORIGIN = 0x3ff9e000 + RESERVE_RTC_FAST, len = 8k - RESERVE_RTC_FAST
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : ORIGIN = 0x50000000 + RESERVE_RTC_SLOW, len = 8k - RESERVE_RTC_SLOW
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/* external memory, including data and text */
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psram_seg(RWX) : ORIGIN = 0x3F500000, len = 0xA80000
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}
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