9a5a546228
* esp32 & esp32s2 sharing scripts * add wokwi files * Add fixup section for esp32s2, fix ordering of sectino includes * Remove debug asm file * Use shared linker scripts for s3 with fixups * Add external.x sections back * Move ld scripts into esp-hal-common * esp32c3 unified linker scripts - rework original c3 script to use the xtensa named sections (e.g, _SECTIONNAME_start) - Add fixups in esp32c3 specific linker - Remove useless text section start and end (not required when using any form of bootloader) * Add RTC alias'. Move some shared fixups to a file * comment and cleanup * unify c2 linker script * unify c6 linker script * remove debug configs * use new esp-riscv-rt * fmt * align db symbol names * fix s3 db
42 lines
985 B
Plaintext
42 lines
985 B
Plaintext
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/* before memory.x to allow override */
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ENTRY(Reset)
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INCLUDE memory.x
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/* after memory.x to allow override */
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PROVIDE(__pre_init = DefaultPreInit);
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PROVIDE(__zero_bss = default_mem_hook);
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PROVIDE(__init_data = default_mem_hook);
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INCLUDE exception.x
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/* map generic regions to output sections */
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INCLUDE "alias.x"
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/* ESP32 fixups */
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INCLUDE "fixups/rtc_fast_rwdata_dummy.x"
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/* END ESP32 fixups */
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/* Shared sections - ordering matters */
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INCLUDE "text.x"
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INCLUDE "rodata.x"
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INCLUDE "rwtext.x"
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INCLUDE "rwdata.x"
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INCLUDE "rtc_fast.x"
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INCLUDE "rtc_slow.x"
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INCLUDE "external.x"
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/* End of Shared sections */
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_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg)-LENGTH(reserved_for_boot_seg) - 2*STACK_SIZE;
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_stack_start_cpu1 = _heap_end;
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_stack_end_cpu1 = _stack_start_cpu1 + STACK_SIZE;
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_stack_start_cpu0 = _stack_end_cpu1;
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_stack_end_cpu0 = _stack_start_cpu0 + STACK_SIZE;
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EXTERN(DefaultHandler);
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EXTERN(WIFI_EVENT); /* Force inclusion of WiFi libraries */
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INCLUDE "device.x" |