99bf346898
* Clean up passing clocks to drivers * Update changelog * Initialise Clocks in a critical section * Fix calling now() before init * Fix doc * Fix esp-wifi migration guide * Add safety comment * Update tests
76 lines
1.6 KiB
Rust
76 lines
1.6 KiB
Rust
//! UART TX/RX Test
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//!
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//! Folowing pins are used:
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//! TX GPIO2 / GPIO9 (esp32s2 and esp32s3)
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//! RX GPIO3 / GPIO10 (esp32s2 and esp32s3)
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//!
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//! Connect TX and RX pins.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use esp_hal::{
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gpio::Io,
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peripherals::{UART0, UART1},
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prelude::*,
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uart::{UartRx, UartTx},
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Blocking,
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};
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use hil_test as _;
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use nb::block;
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struct Context {
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tx: UartTx<'static, UART0, Blocking>,
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rx: UartRx<'static, UART1, Blocking>,
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let (tx, rx) = hil_test::common_test_pins!(io);
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let tx = UartTx::new(peripherals.UART0, tx).unwrap();
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let rx = UartRx::new(peripherals.UART1, rx).unwrap();
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Context { tx, rx }
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}
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#[test]
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#[timeout(3)]
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fn test_send_receive(mut ctx: Context) {
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let byte = [0x42];
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ctx.tx.flush_tx().unwrap();
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ctx.tx.write_bytes(&byte).unwrap();
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let read = block!(ctx.rx.read_byte());
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assert_eq!(read, Ok(0x42));
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}
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#[test]
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#[timeout(3)]
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fn test_send_receive_bytes(mut ctx: Context) {
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let bytes = [0x42, 0x43, 0x44];
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let mut buf = [0u8; 3];
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ctx.tx.flush_tx().unwrap();
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ctx.tx.write_bytes(&bytes).unwrap();
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ctx.rx.read_bytes(&mut buf).unwrap();
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assert_eq!(buf, bytes);
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}
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}
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