99bf346898
* Clean up passing clocks to drivers * Update changelog * Initialise Clocks in a critical section * Fix calling now() before init * Fix doc * Fix esp-wifi migration guide * Add safety comment * Update tests
106 lines
2.6 KiB
Rust
106 lines
2.6 KiB
Rust
//! SPI Full Duplex Test
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//!
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//! Folowing pins are used:
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//! SCLK GPIO0
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//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3)
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//! MOSI GPIO3 / GPIO10 (esp32s2 and esp32s3)
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//! CS GPIO8
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//!
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//! Connect MISO and MOSI pins.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use embedded_hal::spi::SpiBus;
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use esp_hal::{
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gpio::Io,
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prelude::*,
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spi::{master::Spi, FullDuplexMode, SpiMode},
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};
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use hil_test as _;
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struct Context {
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spi: Spi<'static, esp_hal::peripherals::SPI2, FullDuplexMode>,
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio0;
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let (miso, mosi) = hil_test::common_test_pins!(io);
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let cs = io.pins.gpio8;
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let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0).with_pins(
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Some(sclk),
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Some(mosi),
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Some(miso),
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Some(cs),
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);
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Context { spi }
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..])
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.expect("Symmetric transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_asymmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer_huge_buffer(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..]).expect("Huge transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer_huge_buffer_no_alloc(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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ctx.spi
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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}
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}
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