9064177e99
* wip: timg embassy driver - read_raw on timg renamed to now() - timg initialized and stored in static for use in the embassy driver - timg sets alarm value - untested whether alarms actually trigger * TIMG timer driver for esp32, esp32s3 - Adds the timg timer block as a time driver for embassy - Not enabled on the C3 as it only has one timer block, better to use systimer - s2 example added but can't build due to atomic requirements in futures-core * Add S2 atomic support with emulation, fixup embassy support for the S2 * Move executor & static-cell to dev deps. Make eha optional * Add c2 support, run fmt * Update to crates.io embassy releases * Update eha * update timg time driver to new trait * Remove exception feature of esp-backtrace and use the user handler for backtracing * Add async testing workflow * Update systick example * Fix S2 examples * Update xtensa-toolchain * set rustflags for s2 target * Disable systick for esp32s2 until we can fix the noted issues * review improvements - Fix intr prio array being off by one - emabssy time prio interrupt set to max prio - use cfg instead of feature for systick detection * Update example time delays
80 lines
2.0 KiB
Rust
80 lines
2.0 KiB
Rust
//! This demos a simple monitor for the XTAL frequency, by relying on a special
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//! feature of the TIMG0 (Timer Group 0). This feature counts the number of XTAL
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//! clock cycles within a given number of RTC_SLOW_CLK cycles.
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#![no_std]
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#![no_main]
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use core::cell::RefCell;
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use critical_section::Mutex;
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use esp32s2_hal::{
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clock::ClockControl,
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interrupt,
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pac::{self, Peripherals},
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prelude::*,
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Rtc,
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};
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use esp_backtrace as _;
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use xtensa_atomic_emulation_trap as _;
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use esp_println::println;
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use xtensa_lx_rt::entry;
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static RTC: Mutex<RefCell<Option<Rtc>>> = Mutex::new(RefCell::new(None));
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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// Disable watchdog timer
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rtc.rwdt.disable();
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rtc.rwdt.start(2000u64.millis());
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rtc.rwdt.listen();
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println!(
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"{: <10} XTAL frequency: {} MHz",
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"[Expected]",
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clocks.xtal_clock.to_MHz()
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);
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interrupt::enable(pac::Interrupt::RTC_CORE, interrupt::Priority::Priority1).unwrap();
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critical_section::with(|cs| RTC.borrow_ref_mut(cs).replace(rtc));
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loop {}
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}
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#[interrupt]
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fn RTC_CORE() {
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critical_section::with(|cs| {
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let mut rtc = RTC.borrow_ref_mut(cs);
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let rtc = rtc.as_mut().unwrap();
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println!(
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"{: <10} XTAL frequency: {} MHz",
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"[Monitor]",
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rtc.estimate_xtal_frequency()
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);
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rtc.rwdt.clear_interrupt();
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});
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}
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#[xtensa_lx_rt::exception]
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fn exception(cause: xtensa_lx_rt::exception::ExceptionCause, frame: xtensa_lx_rt::exception::Context) {
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use esp_println::*;
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println!("\n\nException occured {:?} {:x?}", cause, frame);
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let backtrace = esp_backtrace::arch::backtrace();
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for b in backtrace.iter() {
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if let Some(addr) = b {
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println!("0x{:x}", addr)
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}
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}
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} |