848029b152
* Mark interconnect as unstable * Explicitly set unstable feature in HIL tests * WIP append feature set name to artifact * Add name to feature sets, build all combinations * Fix tests * Provide a looping executor for stable async tests * Fix usb serial jtag * Hide interconnect types
94 lines
2.2 KiB
Rust
94 lines
2.2 KiB
Rust
//! I2C test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: unstable
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#![no_std]
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#![no_main]
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use esp_hal::{
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i2c::master::{Config, Error, I2c, Operation},
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Async,
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Blocking,
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};
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use hil_test as _;
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struct Context {
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i2c: I2c<'static, Blocking>,
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}
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fn _async_driver_is_compatible_with_blocking_ehal() {
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fn _with_driver(driver: I2c<'static, Async>) {
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_with_ehal(driver);
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}
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fn _with_ehal(_: impl embedded_hal::i2c::I2c) {}
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}
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const DUT_ADDRESS: u8 = 0x77;
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const NON_EXISTENT_ADDRESS: u8 = 0x6b;
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3)]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (sda, scl) = hil_test::i2c_pins!(peripherals);
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// Create a new peripheral object with the described wiring and standard
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// I2C clock speed:
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let i2c = I2c::new(peripherals.I2C0, Config::default())
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.unwrap()
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.with_sda(sda)
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.with_scl(scl);
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Context { i2c }
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}
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#[test]
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fn empty_write_returns_ack_error_for_unknown_address(mut ctx: Context) {
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assert_eq!(
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ctx.i2c.write(NON_EXISTENT_ADDRESS, &[]),
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Err(Error::AckCheckFailed)
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);
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assert_eq!(ctx.i2c.write(DUT_ADDRESS, &[]), Ok(()));
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}
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#[test]
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fn test_read_cali(mut ctx: Context) {
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let mut read_data = [0u8; 22];
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// have a failing read which might could leave the peripheral in an undesirable
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// state
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ctx.i2c
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.write_read(NON_EXISTENT_ADDRESS, &[0xaa], &mut read_data)
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.ok();
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// do the real read which should succeed
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ctx.i2c
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.write_read(DUT_ADDRESS, &[0xaa], &mut read_data)
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.ok();
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assert_ne!(read_data, [0u8; 22])
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}
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#[test]
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fn test_read_cali_with_transactions(mut ctx: Context) {
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let mut read_data = [0u8; 22];
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// do the real read which should succeed
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ctx.i2c
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.transaction(
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DUT_ADDRESS,
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&mut [Operation::Write(&[0xaa]), Operation::Read(&mut read_data)],
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)
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.ok();
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assert_ne!(read_data, [0u8; 22])
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}
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}
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