d6d5e0c86b
* direct vectoring support added * provide minimal handlers for hooking the vector table directly * changed direct vectoring interrupt enable interface to map to CPU interrupt * direct vectoring interrupt nesting * removed unused dependency * added tentative c2 and c6 support for direct vector table hooking * added direct vectoring examples * added direct vectoring examples * updated changelog * added direct vectoring to CI * Added H2 support and example, moved helpers to esp-hal-common * Added H2 direct vectoring example to CI * Removed remnants of removed feature * C6 and H2 examples fixed * C6 and H2 examples fixed * C6 and H2 examples fixed * Comment fixed * Added preemption flag to RT --------- Co-authored-by: Scott Mabin <scott@mabez.dev>
89 lines
2.3 KiB
Rust
89 lines
2.3 KiB
Rust
#![no_main]
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#![no_std]
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#![feature(naked_functions)]
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use core::{arch::asm, cell::RefCell};
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use critical_section::Mutex;
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use esp32c2_hal::{
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clock::ClockControl,
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peripherals::Peripherals,
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prelude::*,
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system::{SoftwareInterrupt, SoftwareInterruptControl},
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timer::TimerGroup,
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Rtc,
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};
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use esp_backtrace as _;
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static SWINT: Mutex<RefCell<Option<SoftwareInterruptControl>>> = Mutex::new(RefCell::new(None));
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#[entry]
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unsafe fn main() -> ! {
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let peripherals = Peripherals::take();
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let mut system = peripherals.SYSTEM.split();
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let clockctrl = system.clock_control;
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let sw_int = system.software_interrupt_control;
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let clocks = ClockControl::boot_defaults(clockctrl).freeze();
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let timer_group0 = TimerGroup::new(
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peripherals.TIMG0,
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&clocks,
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&mut system.peripheral_clock_control,
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);
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let mut wdt0 = timer_group0.wdt;
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// Disable watchdog timers
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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critical_section::with(|cs| SWINT.borrow_ref_mut(cs).replace(sw_int));
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unsafe {
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asm!(
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"
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csrrwi x0, 0x7e0, 1 #what to count, for cycles write 1 for instructions write 2
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csrrwi x0, 0x7e1, 0 #disable counter
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csrrwi x0, 0x7e2, 0 #reset counter
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"
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);
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}
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esp_println::println!("MPC:{}", unsafe { fetch_performance_timer() });
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// interrupt is raised from assembly for max timer granularity.
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unsafe {
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asm!(
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"
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li t0, 0x600C0028 #FROM_CPU_INTR0 address
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li t1, 1 #Flip flag
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csrrwi x0, 0x7e1, 1 #enable timer
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sw t1, 0(t0) #trigger FROM_CPU_INTR0
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"
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)
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}
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esp_println::println!("Returned");
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loop {}
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}
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#[no_mangle]
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fn cpu_int_1_handler() {
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unsafe { asm!("csrrwi x0, 0x7e1, 0 #disable timer") }
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critical_section::with(|cs| {
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SWINT
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.borrow_ref_mut(cs)
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.as_mut()
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.unwrap()
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.reset(SoftwareInterrupt::SoftwareInterrupt0);
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});
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esp_println::println!("Performance counter:{}", unsafe {
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fetch_performance_timer()
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});
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}
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#[naked]
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unsafe extern "C" fn fetch_performance_timer() -> i32 {
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asm!(
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"
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csrr a0, 0x7e2
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jr ra
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",
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options(noreturn)
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);
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}
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