History

Jesse Braham 62ae9dc05c Add `rt-riscv` and `rt-xtensa` features to `esp-hal-common` (#1057 ) * Add `rt-riscv` and `rt-xtensa` features to `esp-hal-common` to allow enabling/disable runtime support * Update the CI workflow to check the chip-specific HAL packages without default features * Update `CHANGELOG.md`		2024-01-03 14:24:05 +00:00
..
.cargo	RISC-V: Make atomic emulation opt-in (#904 )	2023-11-10 11:51:47 +00:00
examples	Don't enable async interrupts without `async` feature (#1042 )	2023-12-19 16:34:17 +00:00
src	Update top-level `README.md`, HAL package documentation (#1017 )	2023-12-12 09:20:53 -08:00
build.rs	Move remaining device-specific linker scripts into `esp-hal-common` (#963 )	2023-11-20 12:25:23 +00:00
Cargo.toml	Add `rt-riscv` and `rt-xtensa` features to `esp-hal-common` (#1057 )	2024-01-03 14:24:05 +00:00
README.md	Update each HAL package's `README`	2023-08-23 07:42:56 -07:00

esp32c2-hal

no_std HAL for the ESP32-C2 from Espressif.

Implements a number of the traits defined in embedded-hal.

This device uses the RISC-V ISA, which is officially supported by the Rust compiler via the riscv32imc-unknown-none-elf target.

Please refer to the documentation for more information.

Resources

Getting Started

Installing the Rust Compiler Target

The compilation target for this device is officially supported by the mainline Rust compiler and can be installed using rustup:

rustup target add riscv32imc-unknown-none-elf

License

Licensed under either of:

Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

README.md