5cca83ca51
Previously it assumed that the entry point was allocated at the beginning of the ".rwtext" output section, which is not always true. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
251 lines
7.9 KiB
Plaintext
251 lines
7.9 KiB
Plaintext
ENTRY(_start_hal)
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PROVIDE(_start_trap = _start_trap_hal);
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PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
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PROVIDE(_max_hart_id = 0);
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PROVIDE(_hart_stack_size = 2K);
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PROVIDE(_heap_size = 0);
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PROVIDE(UserSoft = DefaultHandler);
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PROVIDE(SupervisorSoft = DefaultHandler);
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PROVIDE(MachineSoft = DefaultHandler);
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PROVIDE(UserTimer = DefaultHandler);
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PROVIDE(SupervisorTimer = DefaultHandler);
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PROVIDE(MachineTimer = DefaultHandler);
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PROVIDE(UserExternal = DefaultHandler);
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PROVIDE(SupervisorExternal = DefaultHandler);
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PROVIDE(MachineExternal = DefaultHandler);
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PROVIDE(DefaultHandler = DefaultInterruptHandler);
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PROVIDE(ExceptionHandler = DefaultExceptionHandler);
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/* # Pre-initialization function */
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/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
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then the function this points to will be called before the RAM is initialized. */
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PROVIDE(__pre_init = default_pre_init);
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/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
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PROVIDE(_setup_interrupts = default_setup_interrupts);
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/* # Multi-processing hook function
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fn _mp_hook() -> bool;
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This function is called from all the harts and must return true only for one hart,
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which will perform memory initialization. For other harts it must return false
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and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
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*/
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PROVIDE(_mp_hook = default_mp_hook);
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SECTIONS
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{
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.rodata :
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{
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_srodata = .;
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*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .rodata);
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*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .rodata.*);
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*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .rodata);
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*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .rodata.*);
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*(.srodata .srodata.*);
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*(.rodata .rodata.*);
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/* 4-byte align the end (VMA) of this section.
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This is required by LLD to ensure the LMA of the following .data
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section will have the correct alignment. */
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. = ALIGN(4);
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_erodata = .;
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} > REGION_RODATA AT>ROM
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.rwtext :
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{
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_srwtext = .;
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/* Put reset handler first in .rwtext section so it ends up as the entry */
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/* point of the program. */
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KEEP(*(.init));
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KEEP(*(.init.rust));
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. = ALIGN(4);
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KEEP(*(.trap));
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KEEP(*(.trap.rust));
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*libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
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*libriscv_rt-*.rlib:riscv-rt.*(.literal .text .literal.* .text.*);
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*(.rwtext);
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. = ALIGN(4);
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_erwtext = .;
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} > REGION_RWTEXT AT>ROM
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.rwtext.dummy (NOLOAD):
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{
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/* This section is required to skip .rwtext area because REGION_RWTEXT
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* and REGION_BSS reflect the same address space on different buses.
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*/
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. = ORIGIN(REGION_BSS) + _erwtext - _srwtext;
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} > REGION_BSS
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.bss (NOLOAD) :
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{
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_sbss = .;
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*(.sbss .sbss.* .bss .bss.*);
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. = ALIGN(4);
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_ebss = .;
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} > REGION_BSS
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/* fictitious region that represents the memory available for the heap */
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.heap (NOLOAD) :
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{
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_sheap = .;
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. += _heap_size;
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. = ALIGN(4);
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_eheap = .;
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} > REGION_HEAP
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/* fictitious region that represents the memory available for the stack */
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.stack (NOLOAD) :
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{
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_estack = .;
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. = ABSOLUTE(_stack_start);
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_sstack = .;
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} > REGION_STACK
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.data :
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{
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_sdata = .;
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/* Must be called __global_pointer$ for linker relaxations to work. */
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PROVIDE(__global_pointer$ = . + 0x800);
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*(.sdata .sdata.* .sdata2 .sdata2.*);
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*(.data .data.*);
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*libriscv-*.rlib:riscv.*(.rodata .rodata.*);
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*libriscv_rt-*.rlib:riscv-rt.*(.rodata .rodata.*);
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. = ALIGN(4);
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_edata = .;
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} > REGION_DATA AT>ROM
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.rtc_fast.text :
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{
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_srtc_fast_text = .;
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*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
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. = ALIGN(4);
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_ertc_fast_text = .;
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} > REGION_RTC_FAST AT>ROM
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.rtc_fast.data :
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{
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_rtc_fast_data_start = ABSOLUTE(.);
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*(.rtc_fast.data .rtc_fast.data.*)
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. = ALIGN(4);
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_rtc_fast_data_end = ABSOLUTE(.);
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} > REGION_RTC_FAST AT>ROM
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.rtc_fast.bss (NOLOAD) : ALIGN(4)
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{
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_rtc_fast_bss_start = ABSOLUTE(.);
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*(.rtc_fast.bss .rtc_fast.bss.*)
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. = ALIGN(4);
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_rtc_fast_bss_end = ABSOLUTE(.);
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} > REGION_RTC_FAST
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.rtc_fast.noinit (NOLOAD) : ALIGN(4)
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{
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*(.rtc_fast.noinit .rtc_fast.noinit.*)
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} > REGION_RTC_FAST
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/* The alignment of the "text" output section is forced to
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* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
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* of the next available Flash block.
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* This is required to meet the following constraint from the external
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* flash MMU:
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* VMA % 64KB == LMA % 64KB
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* i.e. the lower 16 bits of both the virtual address (address seen by the
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* CPU) and the load address (physical address of the external flash) must
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* be equal.
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*/
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.text.dummy (NOLOAD) : ALIGN(0x10000)
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{
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/* This section is required to skip .rodata area because REGION_TEXT
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* and REGION_RODATA reflect the same address space on different buses.
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*/
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. += SIZEOF(.rodata);
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} > REGION_TEXT
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.text : ALIGN(0x10000)
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{
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_stext = .;
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*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .text)
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*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .text.*)
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*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .text)
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*(EXCLUDE_FILE (*libriscv_rt-*.rlib:riscv-rt.*) .text.*)
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*(.text .text.*);
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_etext = .;
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} > REGION_TEXT AT>ROM
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/* fake output .got section */
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/* Dynamic relocations are unsupported. This section is only used to detect
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relocatable code in the input files and raise an error if relocatable code
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is found */
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.got (INFO) :
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{
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KEEP(*(.got .got.*));
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}
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.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
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.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
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}
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PROVIDE(_sidata = _erodata + 8);
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PROVIDE(_irwtext = ORIGIN(DROM) + _text_size + _rodata_size + _data_size);
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PROVIDE(_irtc_fast_text = ORIGIN(DROM) + _text_size + _rodata_size + _data_size + _rwtext_size);
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PROVIDE(_irtc_fast_data = ORIGIN(DROM) + _text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size);
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/* Do not exceed this mark in the error messages above | */
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ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
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ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
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ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
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ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
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ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
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ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
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ASSERT(ORIGIN(REGION_HEAP) % 4 == 0, "
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ERROR(riscv-rt): the start of the REGION_HEAP must be 4-byte aligned");
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ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
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ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
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ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
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ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
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ASSERT(_stext % 4 == 0, "
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ERROR(riscv-rt): `_stext` must be 4-byte aligned");
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ASSERT(_sdata % 4 == 0 && _edata % 4 == 0, "
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BUG(riscv-rt): .data is not 4-byte aligned");
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ASSERT(_sidata % 4 == 0, "
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BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
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ASSERT(_sbss % 4 == 0 && _ebss % 4 == 0, "
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BUG(riscv-rt): .bss is not 4-byte aligned");
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ASSERT(_sheap % 4 == 0, "
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BUG(riscv-rt): start of .heap is not 4-byte aligned");
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ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
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ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
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Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
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ASSERT(SIZEOF(.stack) > (_max_hart_id + 1) * _hart_stack_size, "
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ERROR(riscv-rt): .stack section is too small for allocating stacks for all the harts.
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Consider changing `_max_hart_id` or `_hart_stack_size`.");
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ASSERT(SIZEOF(.got) == 0, "
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.got section detected in the input files. Dynamic relocations are not
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supported. If you are linking to C code compiled using the `gcc` crate
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then modify your build script to compile the C code _without_ the
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-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
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details.");
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/* Do not exceed this mark in the error messages above | */
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