esp-hal/esp32s2-hal/src/lib.rs
C2D 59d02f5f6e
Add SHA accelerator implementation (#257)
* Add untested basic SHA for esp-sX/cX chips

* Fix ptr type inconsistency for S2

* Add ESP32 impl & fix process_buffer latch issue

* Add debug example for SHA accelerator

* Clean up no-op buffer prints

* Test vector parity (on esp32s3)

* Checkpoint for converting to alignment helper

* Finish refactoring & additional parity tests on esp32s3

* Remove core_intrinsics requirement for now

* Fix case where (src.len() % 4) == 3

* Finish sha2 example with performance comparison (12-61x speedup)

* Refactor ESP32 to alignment helper & Clean up example

* Prevent out-of-bounds reads in ESP32 version

* Revert Cargo debug changes

* Remove cargo config.toml

* Clean up example

* Remove common/rust-toolchain & ignore in future

* Might as well use actual size_of const

* Remove SHA512/SHA384 for C2/C3

* Directly import nb::block! to remove unused import warning & fix c2 feature detect

* Remove stray newlines

* Fix esp32c2 having SHA256

* ESP32 also has SHA384

* Remove comments that don't have a purpose

* Clean up example & finish() handling

* Add examples & add ESP32 free()

* Update C2/C3 examples to show accurate algorithm used

* Fix busy check for ESP32

* Remove outdated TODO comment

* Update PAC for ESP3 and (actually) fix busy check

* Refactor ESP32 version to reduce search space

* Add debug printlns to sha example & clean up comments

* Fix ESP32 version, finally

Co-authored-by: ferris <ferris@devdroplets.com>
Co-authored-by: Jesse Braham <jesse@beta7.io>
2022-11-28 14:20:31 -08:00

106 lines
2.4 KiB
Rust

#![no_std]
pub use embedded_hal as ehal;
#[doc(inline)]
pub use esp_hal_common::{
clock,
dma,
dma::pdma,
efuse,
gpio as gpio_types,
i2s,
i2c::{self, I2C},
interrupt,
ledc,
macros,
otg_fs,
pac,
prelude,
pulse_control,
serial,
spi,
system,
systimer,
timer,
utils,
Cpu,
Delay,
PulseControl,
Rng,
Rtc,
Rwdt,
Serial,
sha
};
#[cfg(feature = "embassy")]
pub use esp_hal_common::embassy;
pub use self::gpio::IO;
pub mod adc;
pub mod dac;
pub mod gpio;
/// Common module for analog functions
pub mod analog {
pub use esp_hal_common::analog::{AvailableAnalog, SensExt};
}
#[no_mangle]
extern "C" fn EspDefaultHandler(_level: u32, _interrupt: pac::Interrupt) {}
#[no_mangle]
extern "C" fn DefaultHandler() {}
/// Function initializes ESP32 specific memories (RTC slow and fast) and
/// then calls original Reset function
///
/// ENTRY point is defined in memory.x
/// *Note: the pre_init function is called in the original reset handler
/// after the initializations done in this function*
#[cfg(feature = "rt")]
#[doc(hidden)]
#[no_mangle]
pub unsafe extern "C" fn ESP32Reset() -> ! {
// These symbols come from `memory.x`
extern "C" {
static mut _rtc_fast_bss_start: u32;
static mut _rtc_fast_bss_end: u32;
static mut _rtc_slow_bss_start: u32;
static mut _rtc_slow_bss_end: u32;
static mut _stack_end_cpu0: u32;
}
// set stack pointer to end of memory: no need to retain stack up to this point
xtensa_lx::set_stack_pointer(&mut _stack_end_cpu0);
// copying data from flash to various data segments is done by the bootloader
// initialization to zero needs to be done by the application
// Initialize RTC RAM
xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end);
// continue with default reset handler
xtensa_lx_rt::Reset();
}
/// The ESP32 has a first stage bootloader that handles loading program data
/// into the right place therefore we skip loading it again.
#[doc(hidden)]
#[no_mangle]
#[rustfmt::skip]
pub extern "Rust" fn __init_data() -> bool {
false
}
fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
int_enable as u8
| ((nmi_enable as u8) << 1)
| (int_enable as u8) << 2
| ((nmi_enable as u8) << 3)
}