5950a043c0
* Update `embedded-hal-1` and `embedded-hal-nb` dependencies to latest versions * Update the `Delay` and `I2c` trait implementations * Update the `SpiDevice` trait, implement `SpiDeviceRead` and `SpiDeviceWrite`
99 lines
2.5 KiB
Rust
99 lines
2.5 KiB
Rust
//! Delay driver
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//!
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//! Implement the `DelayMs` and `DelayUs` traits from [embedded-hal].
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//!
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//! [embedded-hal]: https://docs.rs/embedded-hal/latest/embedded_hal/
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pub use self::delay::Delay;
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impl<T> embedded_hal::blocking::delay::DelayMs<T> for Delay
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where
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T: Into<u32>,
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{
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fn delay_ms(&mut self, ms: T) {
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for _ in 0..ms.into() {
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self.delay(1000u32);
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}
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}
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}
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impl<T> embedded_hal::blocking::delay::DelayUs<T> for Delay
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where
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T: Into<u32>,
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{
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fn delay_us(&mut self, us: T) {
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self.delay(us.into());
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}
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}
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#[cfg(feature = "eh1")]
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impl embedded_hal_1::delay::DelayUs for Delay {
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fn delay_us(&mut self, us: u32) {
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self.delay(us);
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}
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}
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#[cfg(riscv)]
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mod delay {
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use fugit::HertzU64;
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use crate::{clock::Clocks, systimer::SystemTimer};
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/// Uses the `SYSTIMER` peripheral for counting clock cycles, as
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/// unfortunately the ESP32-C3 does NOT implement the `mcycle` CSR, which is
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/// how we would normally do this.
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pub struct Delay {
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freq: HertzU64,
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}
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impl Delay {
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/// Create a new Delay instance
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pub fn new(clocks: &Clocks) -> Self {
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// The counters and comparators are driven using `XTAL_CLK`. The average clock
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// frequency is fXTAL_CLK/2.5, which is 16 MHz. The timer counting is
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// incremented by 1/16 μs on each `CNT_CLK` cycle.
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Self {
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freq: HertzU64::MHz((clocks.xtal_clock.to_MHz() * 10 / 25) as u64),
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}
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}
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/// Delay for the specified number of microseconds
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pub fn delay(&self, us: u32) {
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let t0 = SystemTimer::now();
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let clocks = (us as u64 * self.freq.raw()) / HertzU64::MHz(1).raw();
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while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {}
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}
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}
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}
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#[cfg(xtensa)]
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mod delay {
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use fugit::HertzU64;
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use crate::clock::Clocks;
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/// Delay driver
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///
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/// Uses the built-in Xtensa timer from the `xtensa_lx` crate.
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pub struct Delay {
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freq: HertzU64,
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}
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impl Delay {
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/// Instantiate the `Delay` driver
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pub fn new(clocks: &Clocks) -> Self {
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Self {
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freq: HertzU64::MHz(clocks.cpu_clock.to_MHz() as u64),
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}
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}
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/// Delay for the specified number of microseconds
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pub fn delay(&self, us: u32) {
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let clocks = (us as u64 * self.freq.raw()) / HertzU64::MHz(1).raw();
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xtensa_lx::timer::delay(clocks as u32);
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}
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}
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}
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