* SPI pins are no longer optional, rename DummyPin * Swap QSPI test expected levels * Tweak documentation around Level, implement PeripheralOutput * Fmt
179 lines
4.8 KiB
Rust
179 lines
4.8 KiB
Rust
//! SPI write and read a flash chip
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//!
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//! The following wiring is assumed:
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//! - SCLK => GPIO0
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//! - MISO => GPIO1
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//! - MOSI => GPIO2
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//! - IO2 => GPIO3
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//! - IO3 => GPIO4
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//! - CS => GPIO5
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//!
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//! The following wiring is assumed for ESP32:
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//! - SCLK => GPIO0
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//! - MISO => GPIO2
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//! - MOSI => GPIO4
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//! - IO2 => GPIO5
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//! - IO3 => GPIO13
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//! - CS => GPIO14
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//!
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//! Depending on your target and the board you are using you have to change the
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//! pins.
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//!
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//! Connect a flash chip (GD25Q64C was used) and make sure QE in the status
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//! register is set.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use esp_backtrace as _;
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use esp_hal::{
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delay::Delay,
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dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
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dma_buffers,
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gpio::Io,
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prelude::*,
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spi::{
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master::{Address, Command, Spi},
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SpiDataMode,
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SpiMode,
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},
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};
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use esp_println::{print, println};
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#[entry]
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fn main() -> ! {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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cfg_if::cfg_if! {
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if #[cfg(feature = "esp32")] {
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let sclk = io.pins.gpio0;
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let miso = io.pins.gpio2;
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let mosi = io.pins.gpio4;
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let sio2 = io.pins.gpio5;
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let sio3 = io.pins.gpio13;
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let cs = io.pins.gpio14;
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} else {
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let sclk = io.pins.gpio0;
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let miso = io.pins.gpio1;
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let mosi = io.pins.gpio2;
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let sio2 = io.pins.gpio3;
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let sio3 = io.pins.gpio4;
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let cs = io.pins.gpio5;
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}
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}
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let dma = Dma::new(peripherals.DMA);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
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let dma_channel = dma.spi2channel;
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} else {
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let dma_channel = dma.channel0;
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}
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}
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(320, 256);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mut spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
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.with_pins(sclk, mosi, miso, sio2, sio3, cs)
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.with_dma(dma_channel.configure(false, DmaPriority::Priority0));
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let delay = Delay::new();
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// write enable
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dma_tx_buf.set_length(0);
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let transfer = spi
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.write(
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SpiDataMode::Single,
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Command::Command8(0x06, SpiDataMode::Single),
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Address::None,
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0,
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dma_tx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_tx_buf) = transfer.wait();
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delay.delay_millis(250);
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// erase sector
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let transfer = spi
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.write(
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SpiDataMode::Single,
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Command::Command8(0x20, SpiDataMode::Single),
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Address::Address24(0x000000, SpiDataMode::Single),
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0,
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dma_tx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_tx_buf) = transfer.wait();
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delay.delay_millis(250);
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// write enable
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let transfer = spi
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.write(
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SpiDataMode::Single,
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Command::Command8(0x06, SpiDataMode::Single),
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Address::None,
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0,
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dma_tx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_tx_buf) = transfer.wait();
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delay.delay_millis(250);
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// write data / program page
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dma_tx_buf.set_length(dma_tx_buf.capacity());
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dma_tx_buf.as_mut_slice().fill(b'!');
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dma_tx_buf.as_mut_slice()[0..][..5].copy_from_slice(&b"Hello"[..]);
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let transfer = spi
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.write(
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SpiDataMode::Quad,
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Command::Command8(0x32, SpiDataMode::Single),
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Address::Address24(0x000000, SpiDataMode::Single),
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0,
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dma_tx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(spi, _) = transfer.wait();
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delay.delay_millis(250);
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loop {
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// quad fast read
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let transfer = spi
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.read(
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SpiDataMode::Quad,
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Command::Command8(0xeb, SpiDataMode::Single),
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Address::Address32(0x000000 << 8, SpiDataMode::Quad),
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4,
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dma_rx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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// here we could do something else while DMA transfer is in progress
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// the buffers and spi is moved into the transfer and we can get it back via
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// `wait`
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(spi, dma_rx_buf) = transfer.wait();
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println!("{:x?}", dma_rx_buf.as_slice());
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for b in &mut dma_rx_buf.as_slice().iter() {
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if *b >= 32 && *b <= 127 {
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print!("{}", *b as char);
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} else {
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print!(".");
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}
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}
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println!();
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delay.delay_millis(250);
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}
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}
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