37466fd9c7
* deep sleep api for esp32 * move to list of wakeup sources * improve Ext0WakeupSource - still WIP * add deep sleep with timer wakeup example add Ext0 wakeup source (WIP/Non-working) * removed alloc (using heapless now) * Sleep: ext0 wakeup working * add sleep_timer_ext0 example * API change: move sleep into RTC as sleep, sleep_deep, sleep_light * fix sleep examples for new API * sleep only implemented for esp32 at this time * sleep only implemented for esp32 at this time * Implement a simple RTCPin trait to support sleep * implement RTCPin for all xtensa SOC * cargo fmt & update changelog * fix change log order (accidentally swaped during rebase) * implement Drop for Ext0WakeupSource * added Ext1 wakeup source * cargo fmt * healpess was unused, removed * fix pase macro usage
774 lines
26 KiB
Rust
774 lines
26 KiB
Rust
use crate::{
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gpio::{
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AlternateFunction,
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GpioPin,
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InterruptStatusRegisterAccess,
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InterruptStatusRegisterAccessBank0,
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InterruptStatusRegisterAccessBank1,
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Unknown,
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},
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peripherals::GPIO,
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Cpu,
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};
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pub const NUM_PINS: usize = 39;
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pub type OutputSignalType = u16;
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pub const OUTPUT_SIGNAL_MAX: u16 = 548;
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pub const INPUT_SIGNAL_MAX: u16 = 539;
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pub const ONE_INPUT: u8 = 0x38;
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pub const ZERO_INPUT: u8 = 0x30;
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pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function2;
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pub(crate) fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO0 {
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unsafe {
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let iomux = &*crate::peripherals::IO_MUX::PTR;
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match gpio_num {
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0 => core::mem::transmute(&(iomux.gpio0)),
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1 => core::mem::transmute(&(iomux.gpio1)),
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2 => core::mem::transmute(&(iomux.gpio2)),
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3 => core::mem::transmute(&(iomux.gpio3)),
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4 => core::mem::transmute(&(iomux.gpio4)),
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5 => core::mem::transmute(&(iomux.gpio5)),
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6 => core::mem::transmute(&(iomux.gpio6)),
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7 => core::mem::transmute(&(iomux.gpio7)),
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8 => core::mem::transmute(&(iomux.gpio8)),
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9 => core::mem::transmute(&(iomux.gpio9)),
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10 => core::mem::transmute(&(iomux.gpio10)),
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11 => core::mem::transmute(&(iomux.gpio11)),
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12 => core::mem::transmute(&(iomux.gpio12)),
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13 => core::mem::transmute(&(iomux.gpio13)),
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14 => core::mem::transmute(&(iomux.gpio14)),
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15 => core::mem::transmute(&(iomux.gpio15)),
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16 => core::mem::transmute(&(iomux.gpio16)),
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17 => core::mem::transmute(&(iomux.gpio17)),
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18 => core::mem::transmute(&(iomux.gpio18)),
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19 => core::mem::transmute(&(iomux.gpio19)),
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20 => core::mem::transmute(&(iomux.gpio20)),
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21 => core::mem::transmute(&(iomux.gpio21)),
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22 => core::mem::transmute(&(iomux.gpio22)),
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23 => core::mem::transmute(&(iomux.gpio23)),
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24 => core::mem::transmute(&(iomux.gpio24)),
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25 => core::mem::transmute(&(iomux.gpio25)),
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26 => core::mem::transmute(&(iomux.gpio26)),
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27 => core::mem::transmute(&(iomux.gpio27)),
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32 => core::mem::transmute(&(iomux.gpio32)),
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33 => core::mem::transmute(&(iomux.gpio33)),
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34 => core::mem::transmute(&(iomux.gpio34)),
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35 => core::mem::transmute(&(iomux.gpio35)),
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36 => core::mem::transmute(&(iomux.gpio36)),
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37 => core::mem::transmute(&(iomux.gpio37)),
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38 => core::mem::transmute(&(iomux.gpio38)),
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39 => core::mem::transmute(&(iomux.gpio39)),
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_ => panic!(),
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}
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}
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}
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pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
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match crate::get_core() {
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Cpu::AppCpu => int_enable as u8 | ((nmi_enable as u8) << 1),
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// this should be bits 3 & 4 respectively, according to the TRM, but it doesn't seem to
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// work. This does though.
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Cpu::ProCpu => (int_enable as u8) << 2 | ((nmi_enable as u8) << 3),
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}
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}
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/// Peripheral input signals for the GPIO mux
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#[allow(non_camel_case_types)]
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#[derive(PartialEq, Copy, Clone)]
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pub enum InputSignal {
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SPICLK = 0,
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SPIQ = 1,
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SPID = 2,
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SPIHD = 3,
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SPIWP = 4,
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SPICS0 = 5,
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SPICS1 = 6,
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SPICS2 = 7,
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HSPICLK = 8,
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HSPIQ = 9,
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HSPID = 10,
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HSPICS0 = 11,
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HSPIHD = 12,
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HSPIWP = 13,
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U0RXD = 14,
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U0CTS = 15,
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U0DSR = 16,
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U1RXD = 17,
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U1CTS = 18,
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I2CM_SDA = 20,
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EXT_I2C_SDA = 22,
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I2S0O_BCK = 23,
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I2S1O_BCK = 24,
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I2S0O_WS = 25,
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I2S1O_WS = 26,
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I2S0I_BCK = 27,
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I2S0I_WS = 28,
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I2CEXT0_SCL = 29,
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I2CEXT0_SDA = 30,
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PWM0_SYNC0 = 31,
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PWM0_SYNC1 = 32,
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PWM0_SYNC2 = 33,
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PWM0_F0 = 34,
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PWM0_F1 = 35,
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PWM0_F2 = 36,
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GPIO_BT_ACTIVE = 37,
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GPIO_BT_PRIORITY = 38,
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PCNT0_SIG_CH0 = 39,
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PCNT0_SIG_CH1 = 40,
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PCNT0_CTRL_CH0 = 41,
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PCNT0_CTRL_CH1 = 42,
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PCNT1_SIG_CH0 = 43,
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PCNT1_SIG_CH1 = 44,
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PCNT1_CTRL_CH0 = 45,
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PCNT1_CTRL_CH1 = 46,
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PCNT2_SIG_CH0 = 47,
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PCNT2_SIG_CH1 = 48,
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PCNT2_CTRL_CH0 = 49,
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PCNT2_CTRL_CH1 = 50,
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PCNT3_SIG_CH0 = 51,
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PCNT3_SIG_CH1 = 52,
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PCNT3_CTRL_CH0 = 53,
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PCNT3_CTRL_CH1 = 54,
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PCNT4_SIG_CH0 = 55,
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PCNT4_SIG_CH1 = 56,
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PCNT4_CTRL_CH0 = 57,
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PCNT4_CTRL_CH1 = 58,
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HSPICS1 = 61,
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HSPICS2 = 62,
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VSPICLK = 63,
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VSPIQ = 64,
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VSPID = 65,
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VSPIHD = 66,
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VSPIWP = 67,
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VSPICS0 = 68,
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VSPICS1 = 69,
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VSPICS2 = 70,
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PCNT5_SIG_CH0 = 71,
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PCNT5_SIG_CH1 = 72,
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PCNT5_CTRL_CH0 = 73,
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PCNT5_CTRL_CH1 = 74,
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PCNT6_SIG_CH0 = 75,
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PCNT6_SIG_CH1 = 76,
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PCNT6_CTRL_CH0 = 77,
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PCNT6_CTRL_CH1 = 78,
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PCNT7_SIG_CH0 = 79,
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PCNT7_SIG_CH1 = 80,
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PCNT7_CTRL_CH0 = 81,
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PCNT7_CTRL_CH1 = 82,
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RMT_SIG_0 = 83,
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RMT_SIG_1 = 84,
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RMT_SIG_2 = 85,
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RMT_SIG_3 = 86,
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RMT_SIG_4 = 87,
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RMT_SIG_5 = 88,
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RMT_SIG_6 = 89,
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RMT_SIG_7 = 90,
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EXT_ADC_START = 93,
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CAN_RX = 94,
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I2CEXT1_SCL = 95,
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I2CEXT1_SDA = 96,
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HOST_CARD_DETECT_N_1 = 97,
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HOST_CARD_DETECT_N_2 = 98,
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HOST_CARD_WRITE_PRT_1 = 99,
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HOST_CARD_WRITE_PRT_2 = 100,
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HOST_CARD_INT_N_1 = 101,
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HOST_CARD_INT_N_2 = 102,
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PWM1_SYNC0 = 103,
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PWM1_SYNC1 = 104,
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PWM1_SYNC2 = 105,
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PWM1_F0 = 106,
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PWM1_F1 = 107,
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PWM1_F2 = 108,
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PWM0_CAP0 = 109,
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PWM0_CAP1 = 110,
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PWM0_CAP2 = 111,
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PWM1_CAP0 = 112,
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PWM1_CAP1 = 113,
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PWM1_CAP2 = 114,
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PWM2_FLTA = 115,
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PWM2_FLTB = 116,
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PWM2_CAP1 = 117,
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PWM2_CAP2 = 118,
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PWM2_CAP3 = 119,
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PWM3_FLTA = 120,
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PWM3_FLTB = 121,
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PWM3_CAP1 = 122,
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PWM3_CAP2 = 123,
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PWM3_CAP3 = 124,
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CAN_CLKOUT = 125,
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SPID4 = 128,
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SPID5 = 129,
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SPID6 = 130,
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SPID7 = 131,
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HSPID4 = 132,
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HSPID5 = 133,
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HSPID6 = 134,
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HSPID7 = 135,
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VSPID4 = 136,
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VSPID5 = 137,
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VSPID6 = 138,
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VSPID7 = 139,
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I2S0I_DATA_0 = 140,
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I2S0I_DATA_1 = 141,
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I2S0I_DATA_2 = 142,
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I2S0I_DATA_3 = 143,
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I2S0I_DATA_4 = 144,
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I2S0I_DATA_5 = 145,
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I2S0I_DATA_6 = 146,
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I2S0I_DATA_7 = 147,
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I2S0I_DATA_8 = 148,
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I2S0I_DATA_9 = 149,
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I2S0I_DATA_10 = 150,
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I2S0I_DATA_11 = 151,
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I2S0I_DATA_12 = 152,
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I2S0I_DATA_13 = 153,
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I2S0I_DATA_14 = 154,
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I2S0I_DATA_15 = 155,
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I2S1I_BCK = 164,
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I2S1I_WS = 165,
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I2S1I_DATA_0 = 166,
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I2S1I_DATA_1 = 167,
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I2S1I_DATA_2 = 168,
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I2S1I_DATA_3 = 169,
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I2S1I_DATA_4 = 170,
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I2S1I_DATA_5 = 171,
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I2S1I_DATA_6 = 172,
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I2S1I_DATA_7 = 173,
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I2S1I_DATA_8 = 174,
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I2S1I_DATA_9 = 175,
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I2S1I_DATA_10 = 176,
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I2S1I_DATA_11 = 177,
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I2S1I_DATA_12 = 178,
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I2S1I_DATA_13 = 179,
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I2S1I_DATA_14 = 180,
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I2S1I_DATA_15 = 181,
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I2S0I_H_SYNC = 190,
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I2S0I_V_SYNC = 191,
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I2S0I_H_ENABLE = 192,
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I2S1I_H_SYNC = 193,
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I2S1I_V_SYNC = 194,
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I2S1I_H_ENABLE = 195,
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U2RXD = 198,
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U2CTS = 199,
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EMAC_MDC = 200,
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EMAC_MDI = 201,
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EMAC_CRS = 202,
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EMAC_COL = 203,
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PCMFSYNC = 204,
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PCMCLK = 205,
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PCMDIN = 206,
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SIG_IN_FUNC224 = 224,
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SIG_IN_FUNC225 = 225,
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SIG_IN_FUNC226 = 226,
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SIG_IN_FUNC227 = 227,
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SIG_IN_FUNC228 = 228,
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SD_DATA0 = 512,
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SD_DATA1,
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SD_DATA2,
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SD_DATA3,
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HS1_DATA0,
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HS1_DATA1,
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HS1_DATA2,
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HS1_DATA3,
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HS1_DATA4,
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HS1_DATA5,
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HS1_DATA6,
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HS1_DATA7,
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HS2_DATA0,
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HS2_DATA1,
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HS2_DATA2,
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HS2_DATA3,
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EMAC_TX_CLK,
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EMAC_RXD2,
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EMAC_TX_ER,
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EMAC_RX_CLK,
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EMAC_RX_ER,
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EMAC_RXD3,
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EMAC_RXD0,
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EMAC_RXD1,
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EMAC_RX_DV,
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MTDI,
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MTCK,
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MTMS,
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}
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/// Peripheral output signals for the GPIO mux
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#[allow(non_camel_case_types)]
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#[derive(PartialEq, Copy, Clone)]
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pub enum OutputSignal {
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SPICLK = 0,
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SPIQ = 1,
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SPID = 2,
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SPIHD = 3,
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SPIWP = 4,
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SPICS0 = 5,
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SPICS1 = 6,
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SPICS2 = 7,
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HSPICLK = 8,
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HSPIQ = 9,
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HSPID = 10,
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HSPICS0 = 11,
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HSPIHD = 12,
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HSPIWP = 13,
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U0TXD = 14,
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U0RTS = 15,
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U0DTR = 16,
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U1TXD = 17,
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U1RTS = 18,
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I2CM_SCL = 19,
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I2CM_SDA = 20,
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EXT2C_SCL = 21,
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EXT2C_SDA = 22,
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I2S0O_BCK = 23,
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I2S1O_BCK = 24,
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I2S0O_WS = 25,
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I2S1O_WS = 26,
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I2S0I_BCK = 27,
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I2S0I_WS = 28,
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I2CEXT0_SCL = 29,
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I2CEXT0_SDA = 30,
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SDIO_TOHOSTT = 31,
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PWM0_0A = 32,
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PWM0_0B = 33,
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PWM0_1A = 34,
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PWM0_1B = 35,
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PWM0_2A = 36,
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PWM0_2B = 37,
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GPIO_WLAN_ACTIVE = 40,
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BB_DIAG0 = 41,
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BB_DIAG1 = 42,
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BB_DIAG2 = 43,
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BB_DIAG3 = 44,
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BB_DIAG4 = 45,
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BB_DIAG5 = 46,
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BB_DIAG6 = 47,
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BB_DIAG7 = 48,
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BB_DIAG8 = 49,
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BB_DIAG9 = 50,
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BB_DIAG10 = 51,
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BB_DIAG11 = 52,
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BB_DIAG12 = 53,
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BB_DIAG13 = 54,
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BB_DIAG14 = 55,
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BB_DIAG15 = 56,
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BB_DIAG16 = 57,
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BB_DIAG17 = 58,
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BB_DIAG18 = 59,
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BB_DIAG19 = 60,
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HSPICS1 = 61,
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HSPICS2 = 62,
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VSPICLK = 63,
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VSPIQ = 64,
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VSPID = 65,
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VSPIHD = 66,
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VSPIWP = 67,
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VSPICS0 = 68,
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VSPICS1 = 69,
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VSPICS2 = 70,
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LEDC_HS_SIG0 = 71,
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LEDC_HS_SIG1 = 72,
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LEDC_HS_SIG2 = 73,
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LEDC_HS_SIG3 = 74,
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LEDC_HS_SIG4 = 75,
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LEDC_HS_SIG5 = 76,
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LEDC_HS_SIG6 = 77,
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LEDC_HS_SIG7 = 78,
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LEDC_LS_SIG0 = 79,
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LEDC_LS_SIG1 = 80,
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LEDC_LS_SIG2 = 81,
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LEDC_LS_SIG3 = 82,
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LEDC_LS_SIG4 = 83,
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LEDC_LS_SIG5 = 84,
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LEDC_LS_SIG6 = 85,
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LEDC_LS_SIG7 = 86,
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RMT_SIG_0 = 87,
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RMT_SIG_1 = 88,
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RMT_SIG_2 = 89,
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RMT_SIG_3 = 90,
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RMT_SIG_4 = 91,
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RMT_SIG_5 = 92,
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RMT_SIG_6 = 93,
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RMT_SIG_7 = 94,
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I2CEXT1_SCL = 95,
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I2CEXT1_SDA = 96,
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HOST_CCMD_OD_PULLUP_EN_N = 97,
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HOST_RST_N_1 = 98,
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HOST_RST_N_2 = 99,
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GPIO_SD0 = 100,
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GPIO_SD1 = 101,
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GPIO_SD2 = 102,
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GPIO_SD3 = 103,
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GPIO_SD4 = 104,
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GPIO_SD5 = 105,
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GPIO_SD6 = 106,
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GPIO_SD7 = 107,
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PWM1_0A = 108,
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PWM1_0B = 109,
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PWM1_1A = 110,
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PWM1_1B = 111,
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PWM1_2A = 112,
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PWM1_2B = 113,
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PWM2_1H = 114,
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PWM2_1L = 115,
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PWM2_2H = 116,
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PWM2_2L = 117,
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PWM2_3H = 118,
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PWM2_3L = 119,
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PWM2_4H = 120,
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PWM2_4L = 121,
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CAN_TX = 123,
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CAN_BUS_OFF_ON = 124,
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SPID4 = 128,
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SPID5 = 129,
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SPID6 = 130,
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SPID7 = 131,
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HSPID4 = 132,
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HSPID5 = 133,
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HSPID6 = 134,
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HSPID7 = 135,
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VSPID4 = 136,
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VSPID5 = 137,
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VSPID6 = 138,
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VSPID7 = 139,
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I2S0O_DATA_0 = 140,
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I2S0O_DATA_1 = 141,
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I2S0O_DATA_2 = 142,
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I2S0O_DATA_3 = 143,
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I2S0O_DATA_4 = 144,
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I2S0O_DATA_5 = 145,
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I2S0O_DATA_6 = 146,
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I2S0O_DATA_7 = 147,
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I2S0O_DATA_8 = 148,
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I2S0O_DATA_9 = 149,
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I2S0O_DATA_10 = 150,
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I2S0O_DATA_11 = 151,
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I2S0O_DATA_12 = 152,
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I2S0O_DATA_13 = 153,
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I2S0O_DATA_14 = 154,
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I2S0O_DATA_15 = 155,
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I2S0O_DATA_16 = 156,
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I2S0O_DATA_17 = 157,
|
|
I2S0O_DATA_18 = 158,
|
|
I2S0O_DATA_19 = 159,
|
|
I2S0O_DATA_20 = 160,
|
|
I2S0O_DATA_21 = 161,
|
|
I2S0O_DATA_22 = 162,
|
|
I2S0O_DATA_23 = 163,
|
|
I2S1I_BCK = 164,
|
|
I2S1I_WS = 165,
|
|
I2S1O_DATA_0 = 166,
|
|
I2S1O_DATA_1 = 167,
|
|
I2S1O_DATA_2 = 168,
|
|
I2S1O_DATA_3 = 169,
|
|
I2S1O_DATA_4 = 170,
|
|
I2S1O_DATA_5 = 171,
|
|
I2S1O_DATA_6 = 172,
|
|
I2S1O_DATA_7 = 173,
|
|
I2S1O_DATA_8 = 174,
|
|
I2S1O_DATA_9 = 175,
|
|
I2S1O_DATA_10 = 176,
|
|
I2S1O_DATA_11 = 177,
|
|
I2S1O_DATA_12 = 178,
|
|
I2S1O_DATA_13 = 179,
|
|
I2S1O_DATA_14 = 180,
|
|
I2S1O_DATA_15 = 181,
|
|
I2S1O_DATA_16 = 182,
|
|
I2S1O_DATA_17 = 183,
|
|
I2S1O_DATA_18 = 184,
|
|
I2S1O_DATA_19 = 185,
|
|
I2S1O_DATA_20 = 186,
|
|
I2S1O_DATA_21 = 187,
|
|
I2S1O_DATA_22 = 188,
|
|
I2S1O_DATA_23 = 189,
|
|
PWM3_1H = 190,
|
|
PWM3_1L = 191,
|
|
PWM3_2H = 192,
|
|
PWM3_2L = 193,
|
|
PWM3_3H = 194,
|
|
PWM3_3L = 195,
|
|
PWM3_4H = 196,
|
|
PWM3_4L = 197,
|
|
U2TXD = 198,
|
|
U2RTS = 199,
|
|
EMAC_MDC = 200,
|
|
EMAC_MDO = 201,
|
|
EMAC_CRS = 202,
|
|
EMAC_COL = 203,
|
|
BT_AUDIO0RQ = 204,
|
|
BT_AUDIO1RQ = 205,
|
|
BT_AUDIO2RQ = 206,
|
|
BLE_AUDIO0RQ = 207,
|
|
BLE_AUDIO1RQ = 208,
|
|
BLE_AUDIO2RQ = 209,
|
|
PCMFSYNC = 210,
|
|
PCMCLK = 211,
|
|
PCMDOUT = 212,
|
|
BLE_AUDIO_SYNC0_P = 213,
|
|
BLE_AUDIO_SYNC1_P = 214,
|
|
BLE_AUDIO_SYNC2_P = 215,
|
|
ANT_SEL0 = 216,
|
|
ANT_SEL1 = 217,
|
|
ANT_SEL2 = 218,
|
|
ANT_SEL3 = 219,
|
|
ANT_SEL4 = 220,
|
|
ANT_SEL5 = 221,
|
|
ANT_SEL6 = 222,
|
|
ANT_SEL7 = 223,
|
|
SIGNAL_224 = 224,
|
|
SIGNAL_225 = 225,
|
|
SIGNAL_226 = 226,
|
|
SIGNAL_227 = 227,
|
|
SIGNAL_228 = 228,
|
|
GPIO = 256,
|
|
|
|
CLK_OUT1 = 512,
|
|
CLK_OUT2,
|
|
CLK_OUT3,
|
|
SD_CLK,
|
|
SD_CMD,
|
|
SD_DATA0,
|
|
SD_DATA1,
|
|
SD_DATA2,
|
|
SD_DATA3,
|
|
HS1_CLK,
|
|
HS1_CMD,
|
|
HS1_DATA0,
|
|
HS1_DATA1,
|
|
HS1_DATA2,
|
|
HS1_DATA3,
|
|
HS1_DATA4,
|
|
HS1_DATA5,
|
|
HS1_DATA6,
|
|
HS1_DATA7,
|
|
HS1_STROBE,
|
|
HS2_CLK,
|
|
HS2_CMD,
|
|
HS2_DATA0,
|
|
HS2_DATA1,
|
|
HS2_DATA2,
|
|
HS2_DATA3,
|
|
|
|
EMAC_TX_CLK,
|
|
EMAC_TX_ER,
|
|
EMAC_TXD3,
|
|
EMAC_RX_ER,
|
|
EMAC_TXD2,
|
|
EMAC_CLK_OUT,
|
|
EMAC_CLK_180,
|
|
EMAC_TXD0,
|
|
EMAC_TX_EN,
|
|
EMAC_TXD1,
|
|
|
|
MTDO,
|
|
}
|
|
|
|
pub(crate) fn errata36(pin_num: u8, pull_up: bool, pull_down: bool) {
|
|
use crate::peripherals::RTC_IO;
|
|
let rtcio = unsafe { &*RTC_IO::PTR };
|
|
|
|
match pin_num {
|
|
0 => {
|
|
rtcio
|
|
.touch_pad1
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
2 => {
|
|
rtcio
|
|
.touch_pad2
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
4 => {
|
|
rtcio
|
|
.touch_pad0
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
12 => {
|
|
rtcio
|
|
.touch_pad5
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
13 => {
|
|
rtcio
|
|
.touch_pad4
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
14 => {
|
|
rtcio
|
|
.touch_pad6
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
15 => {
|
|
rtcio
|
|
.touch_pad3
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
25 => {
|
|
rtcio.pad_dac1.modify(|r, w| unsafe {
|
|
w.bits(r.bits())
|
|
.pdac1_rue()
|
|
.bit(pull_up)
|
|
.pdac1_rde()
|
|
.bit(pull_down)
|
|
});
|
|
}
|
|
26 => {
|
|
rtcio.pad_dac2.modify(|r, w| unsafe {
|
|
w.bits(r.bits())
|
|
.pdac2_rue()
|
|
.bit(pull_up)
|
|
.pdac2_rde()
|
|
.bit(pull_down)
|
|
});
|
|
}
|
|
27 => {
|
|
rtcio
|
|
.touch_pad7
|
|
.modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) });
|
|
}
|
|
32 => {
|
|
rtcio.xtal_32k_pad.modify(|r, w| unsafe {
|
|
w.bits(r.bits())
|
|
.x32n_rue()
|
|
.bit(pull_up)
|
|
.x32n_rde()
|
|
.bit(pull_down)
|
|
});
|
|
}
|
|
33 => {
|
|
rtcio.xtal_32k_pad.modify(|r, w| unsafe {
|
|
w.bits(r.bits())
|
|
.x32p_rue()
|
|
.bit(pull_up)
|
|
.x32p_rde()
|
|
.bit(pull_down)
|
|
});
|
|
}
|
|
_ => (),
|
|
}
|
|
}
|
|
|
|
crate::gpio::gpio! {
|
|
(0, 0, InputOutputAnalog (5 => EMAC_TX_CLK) (1 => CLK_OUT1))
|
|
(1, 0, InputOutput (5 => EMAC_RXD2) (0 => U0TXD 1 => CLK_OUT3))
|
|
(2, 0, InputOutputAnalog (1 => HSPIWP 3 => HS2_DATA0 4 => SD_DATA0) (3 => HS2_DATA0 4 => SD_DATA0))
|
|
(3, 0, InputOutput (0 => U0RXD) (1 => CLK_OUT2))
|
|
(4, 0, InputOutput (1 => HSPIHD 3 => HS2_DATA1 4 => SD_DATA1 5 => EMAC_TX_ER) (3 => HS2_DATA1 4 => SD_DATA1))
|
|
(5, 0, InputOutput (1 => VSPICS0 3 => HS1_DATA6 5 => EMAC_RX_CLK) (3 => HS1_DATA6))
|
|
(6, 0, InputOutput (4 => U1CTS) (0 => SD_CLK 1 => SPICLK 3 => HS1_CLK))
|
|
(7, 0, InputOutput (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0) (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0 4 => U2RTS))
|
|
(8, 0, InputOutput (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1 4 => U2CTS) (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1))
|
|
(9, 0, InputOutput (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2 4 => U1RXD) (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2))
|
|
(10, 0, InputOutput ( 0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3) (0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3 4 => U1TXD))
|
|
(11, 0, InputOutput ( 1 => SPICS0) (0 => SD_CMD 1 => SPICS0 3 => HS1_CMD 4 => U1RTS))
|
|
(12, 0, InputOutputAnalog (0 => MTDI 1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2) (1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2 5 => EMAC_TXD3))
|
|
(13, 0, InputOutputAnalog (0 => MTCK 1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3) (1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3 5 => EMAC_RX_ER))
|
|
(14, 0, InputOutputAnalog (0 => MTMS 1 => HSPICLK) (1 => HSPICLK 3 => HS2_CLK 4 => SD_CLK 5 => EMAC_TXD2))
|
|
(15, 0, InputOutputAnalog (1 => HSPICS0 5 => EMAC_RXD3) (0 => MTDO 1 => HSPICS0 3 => HS2_CMD 4 => SD_CMD))
|
|
(16, 0, InputOutput (3 => HS1_DATA4 4 => U2RXD) (3 => HS1_DATA4 5 => EMAC_CLK_OUT))
|
|
(17, 0, InputOutput (3 => HS1_DATA5) (3 => HS1_DATA5 4 => U2TXD 5 => EMAC_CLK_180))
|
|
(18, 0, InputOutput (1 => VSPICLK 3 => HS1_DATA7) (1 => VSPICLK 3 => HS1_DATA7))
|
|
(19, 0, InputOutput (1 => VSPIQ 3 => U0CTS) (1 => VSPIQ 5 => EMAC_TXD0))
|
|
(20, 0, InputOutput)
|
|
(21, 0, InputOutput (1 => VSPIHD) (1 => VSPIHD 5 => EMAC_TX_EN))
|
|
(22, 0, InputOutput (1 => VSPIWP) (1 => VSPIWP 3 => U0RTS 5 => EMAC_TXD1))
|
|
(23, 0, InputOutput (1 => VSPID) (1 => VSPID 3 => HS1_STROBE))
|
|
(24, 0, InputOutput)
|
|
(25, 0, InputOutputAnalog (5 => EMAC_RXD0) ())
|
|
(26, 0, InputOutputAnalog (5 => EMAC_RXD1) ())
|
|
(27, 0, InputOutputAnalog (5 => EMAC_RX_DV) ())
|
|
(32, 1, InputOutputAnalog)
|
|
(33, 1, InputOutputAnalog)
|
|
(34, 1, InputOnlyAnalog)
|
|
(35, 1, InputOnlyAnalog)
|
|
(36, 1, InputOnlyAnalog)
|
|
(37, 1, InputOnlyAnalog)
|
|
(38, 1, InputOnlyAnalog)
|
|
(39, 1, InputOnlyAnalog)
|
|
}
|
|
|
|
crate::gpio::analog! {
|
|
(36, 0, sensor_pads, sense1_mux_sel, sense1_fun_sel, sense1_fun_ie)
|
|
(37, 1, sensor_pads, sense2_mux_sel, sense2_fun_sel, sense2_fun_ie)
|
|
(38, 2, sensor_pads, sense3_mux_sel, sense3_fun_sel, sense3_fun_ie)
|
|
(39, 3, sensor_pads, sense4_mux_sel, sense4_fun_sel, sense4_fun_ie)
|
|
(34, 4, adc_pad, adc1_mux_sel, adc1_fun_sel, adc1_fun_ie)
|
|
(35, 5, adc_pad, adc2_mux_sel, adc2_fun_sel, adc1_fun_ie)
|
|
(25, 6, pad_dac1, pdac1_mux_sel, pdac1_fun_sel, pdac1_fun_ie, pdac1_rue, pdac1_rde)
|
|
(26, 7, pad_dac2, pdac2_mux_sel, pdac2_fun_sel, pdac2_fun_ie, pdac2_rue, pdac2_rde)
|
|
(33, 8, xtal_32k_pad, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_rue, x32n_rde )
|
|
(32, 9, xtal_32k_pad, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_rue, x32p_rde )
|
|
(4, 10, touch_pad0, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(0, 11, touch_pad1, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(2, 12, touch_pad2, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(15, 13, touch_pad3, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(13, 14, touch_pad4, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(12, 15, touch_pad5, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(14, 16, touch_pad6, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
(27, 17, touch_pad7, mux_sel, fun_sel, fun_ie, rue, rde )
|
|
}
|
|
|
|
crate::gpio::rtc_pins! {
|
|
(36, 0, sensor_pads, sense1_ )
|
|
(37, 1, sensor_pads, sense2_ )
|
|
(38, 2, sensor_pads, sense3_ )
|
|
(39, 3, sensor_pads, sense4_ )
|
|
(34, 4, adc_pad, adc1_ )
|
|
(35, 5, adc_pad, adc2_ )
|
|
(25, 6, pad_dac1, pdac1_ )
|
|
(26, 7, pad_dac2, pdac2_ )
|
|
(33, 8, xtal_32k_pad, x32n_ )
|
|
(32, 9, xtal_32k_pad, x32p_ )
|
|
(4, 10, touch_pad0, "")
|
|
(0, 11, touch_pad1, "")
|
|
(2, 12, touch_pad2, "")
|
|
(15, 13, touch_pad3, "")
|
|
(13, 14, touch_pad4, "")
|
|
(12, 15, touch_pad5, "")
|
|
(14, 16, touch_pad6, "")
|
|
(27, 17, touch_pad7, "")
|
|
}
|
|
|
|
impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
|
|
fn pro_cpu_interrupt_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.pcpu_int.read().bits()
|
|
}
|
|
|
|
fn pro_cpu_nmi_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.pcpu_nmi_int.read().bits()
|
|
}
|
|
|
|
fn app_cpu_interrupt_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.acpu_int.read().bits()
|
|
}
|
|
|
|
fn app_cpu_nmi_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.acpu_nmi_int.read().bits()
|
|
}
|
|
}
|
|
|
|
impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
|
|
fn pro_cpu_interrupt_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.pcpu_int1.read().bits()
|
|
}
|
|
|
|
fn pro_cpu_nmi_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.pcpu_nmi_int1.read().bits()
|
|
}
|
|
|
|
fn app_cpu_interrupt_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.acpu_int1.read().bits()
|
|
}
|
|
|
|
fn app_cpu_nmi_status_read() -> u32 {
|
|
unsafe { &*GPIO::PTR }.acpu_nmi_int1.read().bits()
|
|
}
|
|
}
|