9a5a546228
* esp32 & esp32s2 sharing scripts * add wokwi files * Add fixup section for esp32s2, fix ordering of sectino includes * Remove debug asm file * Use shared linker scripts for s3 with fixups * Add external.x sections back * Move ld scripts into esp-hal-common * esp32c3 unified linker scripts - rework original c3 script to use the xtensa named sections (e.g, _SECTIONNAME_start) - Add fixups in esp32c3 specific linker - Remove useless text section start and end (not required when using any form of bootloader) * Add RTC alias'. Move some shared fixups to a file * comment and cleanup * unify c2 linker script * unify c6 linker script * remove debug configs * use new esp-riscv-rt * fmt * align db symbol names * fix s3 db
30 lines
645 B
Plaintext
30 lines
645 B
Plaintext
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SECTIONS {
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.rtc_slow.text : {
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. = ALIGN(4);
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*(.rtc_slow.literal .rtc_slow.text .rtc_slow.literal.* .rtc_slow.text.*)
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} > rtc_slow_seg AT > RODATA
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.rtc_slow.data :
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{
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. = ALIGN(4);
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_rtc_slow_data_start = ABSOLUTE(.);
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*(.rtc_slow.data .rtc_slow.data.*)
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_rtc_slow_data_end = ABSOLUTE(.);
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} > rtc_slow_seg AT > RODATA
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.rtc_slow.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_rtc_slow_bss_start = ABSOLUTE(.);
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*(.rtc_slow.bss .rtc_slow.bss.*)
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_rtc_slow_bss_end = ABSOLUTE(.);
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} > rtc_slow_seg
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.rtc_slow.noinit (NOLOAD) :
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{
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. = ALIGN(4);
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*(.rtc_slow.noinit .rtc_slow.noinit.*)
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} > rtc_slow_seg
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} |