* Initial documentation improvements * More documentation improvements * More documentation improvements More modules documented * Finished SOC documentation for esp32 + TWAI * Fix: fix incorrect formatting * Adding more documentation to rom, and soc peripherals for multiple chips * Adding documentation for multiple peripherals * Adding SOC module documentation * Analog and clock modules are documented * Adding module-level documentation for DMA and INTERRUPT peripherals * Finishing job + minor fixes * Fix unopened HTML break * Rustfmt adjustment formatting Fix typo * Add CHANGELOG record Fix typo * Fix typos, mistakes, improving docs Co-authored-by: Dániel Buga <bugadani@gmail.com> Fix typo Co-authored-by: Dániel Buga <bugadani@gmail.com> Fix typo Co-authored-by: Dániel Buga <bugadani@gmail.com> Fix typo Co-authored-by: Dániel Buga <bugadani@gmail.com> fix typo Co-authored-by: Dániel Buga <bugadani@gmail.com> Fix typo Co-authored-by: Dániel Buga <bugadani@gmail.com> Fix typo Co-authored-by: Scott Mabin <scott@mabez.dev> Fixing typos, mistakes, improving docs. * Fix formatting, mistakes and typos * Fixing a bunch of logical, grammatical and formatting mistakes
139 lines
4.3 KiB
Rust
139 lines
4.3 KiB
Rust
//! # Radio clocks driver (ESP32)
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//!
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//! ## Overview
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//!
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//! The `Radio Clocks` module provides control and configuration functions for
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//! various radio peripherals, such as `PHY`, `Bluetooth (BT)`, and `Wi-Fi`. The
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//! module allows enabling and disabling these peripherals, resetting the `Media
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//! Access Control (MAC)` and initializing clocks.
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//!
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//! The module defines a `RadioClockController` trait implemented by the
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//! `RadioClockControl` struct. This trait provides methods to enable, disable,
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//! reset the MAC, initialize clocks and perform other related operations.
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use crate::system::{RadioClockControl, RadioClockController, RadioPeripherals};
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const DPORT_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x000003c9;
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const DPORT_WIFI_CLK_WIFI_EN_M: u32 = 0x00000406;
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const DPORT_WIFI_CLK_BT_EN_M: u32 = 0x00030800;
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impl RadioClockController for RadioClockControl {
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fn enable(&mut self, peripheral: RadioPeripherals) {
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match peripheral {
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RadioPeripherals::Phy => enable_phy(),
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RadioPeripherals::Bt => bt_clock_enable(),
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RadioPeripherals::Wifi => wifi_clock_enable(),
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}
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}
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fn disable(&mut self, peripheral: RadioPeripherals) {
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match peripheral {
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RadioPeripherals::Phy => disable_phy(),
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RadioPeripherals::Bt => bt_clock_disable(),
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RadioPeripherals::Wifi => wifi_clock_disable(),
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}
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}
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fn reset_mac(&mut self) {
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reset_mac();
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}
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fn init_clocks(&mut self) {
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init_clocks();
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}
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fn ble_rtc_clk_init(&mut self) {
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// nothing for this target
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}
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fn reset_rpa(&mut self) {
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// nothing for this target
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}
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}
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fn enable_phy() {
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// `periph_ll_wifi_bt_module_enable_clk_clear_rst`
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.wifi_clk_en
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.modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M) });
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}
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fn disable_phy() {
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// `periph_ll_wifi_bt_module_disable_clk_set_rst`
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.wifi_clk_en
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.modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M) });
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}
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fn bt_clock_enable() {
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.wifi_clk_en
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.modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_BT_EN_M) });
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}
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fn bt_clock_disable() {
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.wifi_clk_en
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.modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_BT_EN_M) });
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}
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fn wifi_clock_enable() {
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// `periph_ll_wifi_module_enable_clk_clear_rst`
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.wifi_clk_en
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.modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M) });
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}
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fn wifi_clock_disable() {
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// `periph_ll_wifi_module_disable_clk_set_rst`
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.wifi_clk_en
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.modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M) });
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}
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fn reset_mac() {
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const SYSTEM_MAC_RST: u8 = 1 << 2;
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let dport = unsafe { &*esp32::DPORT::PTR };
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dport
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.core_rst_en
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.modify(|r, w| unsafe { w.core_rst().bits(r.core_rst().bits() | SYSTEM_MAC_RST) });
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dport
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.core_rst_en
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.modify(|r, w| unsafe { w.core_rst().bits(r.core_rst().bits() & !SYSTEM_MAC_RST) });
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}
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fn init_clocks() {
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let dport = unsafe { &*esp32::DPORT::PTR };
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// esp-idf assumes all clocks are enabled by default, and disables the following
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// bits:
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//
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// ```
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// const DPORT_WIFI_CLK_SDIOSLAVE_EN: u32 = 1 << 4;
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// const DPORT_WIFI_CLK_UNUSED_BIT5: u32 = 1 << 5;
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// const DPORT_WIFI_CLK_UNUSED_BIT12: u32 = 1 << 12;
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// const DPORT_WIFI_CLK_SDIO_HOST_EN: u32 = 1 << 13;
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// const DPORT_WIFI_CLK_EMAC_EN: u32 = 1 << 14;
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//
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// const WIFI_BT_SDIO_CLK: u32 = DPORT_WIFI_CLK_WIFI_EN_M
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// | DPORT_WIFI_CLK_BT_EN_M
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// | DPORT_WIFI_CLK_UNUSED_BIT5
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// | DPORT_WIFI_CLK_UNUSED_BIT12
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// | DPORT_WIFI_CLK_SDIOSLAVE_EN
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// | DPORT_WIFI_CLK_SDIO_HOST_EN
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// | DPORT_WIFI_CLK_EMAC_EN;
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// ```
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//
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// However, we can't do this because somehow our initialization process is
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// different, and disabling some bits, or not enabling them makes the BT
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// stack crash.
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dport.wifi_clk_en.write(|w| unsafe { w.bits(u32::MAX) });
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}
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