156 lines
4.1 KiB
Rust
156 lines
4.1 KiB
Rust
//! SPI Full Duplex Test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use embedded_hal::spi::SpiBus;
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#[cfg(pcnt)]
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use esp_hal::{
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gpio::interconnect::InputSignal,
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pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
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};
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use esp_hal::{
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gpio::Io,
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peripherals::SPI2,
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prelude::*,
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spi::{master::Spi, FullDuplexMode, SpiMode},
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};
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use hil_test as _;
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struct Context {
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spi: Spi<'static, SPI2, FullDuplexMode>,
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#[cfg(pcnt)]
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pcnt_source: InputSignal,
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#[cfg(pcnt)]
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pcnt_unit: Unit<'static, 0>,
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio0;
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let (_, mosi) = hil_test::common_test_pins!(io);
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let mosi_loopback = mosi.peripheral_input();
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#[cfg(pcnt)]
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let mosi_loopback_pcnt = mosi.peripheral_input();
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let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
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.with_sck(sclk)
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.with_mosi(mosi)
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.with_miso(mosi_loopback);
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#[cfg(pcnt)]
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let pcnt = Pcnt::new(peripherals.PCNT);
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Context {
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spi,
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#[cfg(pcnt)]
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pcnt_source: mosi_loopback_pcnt,
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#[cfg(pcnt)]
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pcnt_unit: pcnt.unit0,
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}
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..])
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.expect("Symmetric transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_asymmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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fn test_asymmetric_write(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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SpiBus::write(&mut ctx.spi, &write[..]).expect("Asymmetric write failed");
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// Flush because we're not reading, so the write may happen in the background
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ctx.spi.flush().expect("Flush failed");
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assert_eq!(unit.get_value(), 9);
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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fn test_asymmetric_write_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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SpiBus::transfer(&mut ctx.spi, &mut [], &write[..]).expect("Asymmetric transfer failed");
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// Flush because we're not reading, so the write may happen in the background
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ctx.spi.flush().expect("Flush failed");
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assert_eq!(unit.get_value(), 9);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer_huge_buffer(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..]).expect("Huge transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer_huge_buffer_no_alloc(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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ctx.spi
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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}
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}
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