esp-hal/esp32h2-hal
Kirill Mikhailov 24c5e8cb79
Adding async support for RSA peripheral (#790)
* Adding async support for RSA peripheral

* Add esp32 support (doesn't work properly yet)

* Xtensa chips are supported (except of esp32)

Add modular multiplication for esp32

Adding a CHANGELOG entry

Rebase issue fix

* Code cleanup

* Add `.await` on `RsaFuture::new()` calls

* Refactor and rebase

Made `read_results` functions to be `async`, got rid of `nb` usage

* Change API methods naming + refactor `start_step2` method

* Adjust example to the API change + documentation

* Code cleaning + refactoring

Update examples
2023-09-27 09:03:06 -07:00
..
.cargo Started adding ESP32-H2 support (#482) 2023-05-08 08:03:08 -07:00
examples Adding async support for RSA peripheral (#790) 2023-09-27 09:03:06 -07:00
ld Remove heap related symbols, use all remaining memory for the stack (#716) 2023-08-14 13:38:36 +02:00
src Add defmt support, make log optional (#773) 2023-09-04 11:29:44 +01:00
build.rs Started adding ESP32-H2 support (#482) 2023-05-08 08:03:08 -07:00
Cargo.toml Async PARL_IO support (#807) 2023-09-21 17:34:53 +02:00
README.md Update each HAL package's README 2023-08-23 07:42:56 -07:00

esp32h2-hal

Crates.io docs.rs Crates.io Matrix

no_std HAL for the ESP32-H2 from Espressif.

Implements a number of the traits defined in embedded-hal.

This device uses the RISC-V ISA, which is officially supported by the Rust compiler via the riscv32imac-unknown-none-elf target.

Please refer to the documentation for more information.

Documentation

Resources

Getting Started

Installing the Rust Compiler Target

The compilation target for this device is officially supported by the mainline Rust compiler and can be installed using rustup:

rustup target add riscv32imac-unknown-none-elf

License

Licensed under either of:

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.