19db509403
* Get rid of missing docs in a number of modules * address reviews * Address the rest of reviews * remove all remaining `allows` * are you serious?
51 lines
1.3 KiB
Rust
51 lines
1.3 KiB
Rust
//! # SOC (System-on-Chip) module (ESP32-C2)
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//!
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//! ## Overview
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//!
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//! The `SOC` module provides access, functions and structures that are useful
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//! for interacting with various system-related peripherals on `ESP32-C2` chip.
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use self::peripherals::{LPWR, TIMG0};
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use crate::{rtc_cntl::Rtc, timer::timg::Wdt};
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pub mod efuse;
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pub mod gpio;
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pub mod peripherals;
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pub mod radio_clocks;
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pub mod trng;
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/// The name of the chip ("esp32c2") as `&str`
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#[macro_export]
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macro_rules! chip {
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() => {
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"esp32c2"
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};
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}
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pub use chip;
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#[allow(unused)]
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pub(crate) mod registers {
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pub const INTERRUPT_MAP_BASE: u32 = 0x600c2000;
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}
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pub(crate) mod constants {
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/// The lower bound of the system's DRAM (Data RAM) address space.
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pub const SOC_DRAM_LOW: u32 = 0x3FCA_0000;
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/// The upper bound of the system's DRAM (Data RAM) address space.
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pub const SOC_DRAM_HIGH: u32 = 0x3FCE_0000;
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/// RC FAST Clock value (Hertz).
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pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500);
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}
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#[export_name = "__post_init"]
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unsafe fn post_init() {
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// RTC domain must be enabled before we try to disable
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let mut rtc = Rtc::new(LPWR::steal());
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rtc.swd.disable();
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rtc.rwdt.disable();
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Wdt::<TIMG0, crate::Blocking>::set_wdt_enabled(false);
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}
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