1424f2a43d
* Implement `InterruptConfigurable` * Fix doc-tests * Clippy * Fix lp_core_uart example * CHANGELOG.md * Have DEFAULT_INTERRUPT_HANDLER * Fix docs * Clippy * Add `set_interrupt_handler` for WDT
53 lines
1.2 KiB
Rust
53 lines
1.2 KiB
Rust
//! Clock Monitor Test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use defmt_rtt as _;
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use esp_backtrace as _;
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use esp_hal::{
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clock::ClockControl,
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peripherals::Peripherals,
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rtc_cntl::Rtc,
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system::SystemControl,
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};
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struct Context<'a> {
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rtc: Rtc<'a>,
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}
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impl Context<'_> {
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pub fn init() -> Self {
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let peripherals = Peripherals::take();
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let system = SystemControl::new(peripherals.SYSTEM);
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ClockControl::boot_defaults(system.clock_control).freeze();
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let rtc = Rtc::new(peripherals.LPWR);
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Context { rtc }
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}
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context<'static> {
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Context::init()
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}
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#[test]
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fn test_estimated_clock(mut ctx: Context<'static>) {
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#[cfg(feature = "esp32c2")] // 26 MHz
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defmt::assert!((23..=29).contains(&ctx.rtc.estimate_xtal_frequency()));
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#[cfg(feature = "esp32h2")] // 32 MHz
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defmt::assert!((29..=35).contains(&ctx.rtc.estimate_xtal_frequency()));
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#[cfg(not(any(feature = "esp32h2", feature = "esp32c2")))] // 40 MHz
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defmt::assert!((35..=45).contains(&ctx.rtc.estimate_xtal_frequency()));
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}
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}
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