bbe1e5df59
* ESP32-C6 LP CORE delay and basic gpio * CHANGELOG.md, build LP examples in release mode
86 lines
1.8 KiB
Rust
86 lines
1.8 KiB
Rust
#![no_std]
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use core::arch::global_asm;
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pub mod delay;
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pub mod gpio;
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pub mod riscv {
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//! Low level access to RISC-V processors.
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//!
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//! Re-exports <https://crates.io/crates/riscv>
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pub use riscv::*;
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}
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pub mod prelude;
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const CPU_CLOCK: u32 = 16_000_000;
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global_asm!(
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r#"
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.section .init.vector, "ax"
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/* This is the vector table. It is currently empty, but will be populated
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* with exception and interrupt handlers when this is supported
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*/
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.align 0x4, 0xff
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.global _vector_table
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.type _vector_table, @function
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_vector_table:
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.option push
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.option norvc
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.rept 32
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nop
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.endr
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.option pop
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.size _vector_table, .-_vector_table
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.section .init, "ax"
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.global reset_vector
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/* The reset vector, jumps to startup code */
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reset_vector:
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j __start
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__start:
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/* setup the stack pointer */
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la sp, __stack_top
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call lp_core_startup
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loop:
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j loop
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"#
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);
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#[link_section = ".init.rust"]
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#[export_name = "lp_core_startup"]
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unsafe extern "C" fn lp_core_startup() -> ! {
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extern "Rust" {
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fn main() -> !;
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}
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main();
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}
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mod critical_section_impl {
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struct CriticalSection;
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critical_section::set_impl!(CriticalSection);
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unsafe impl critical_section::Impl for CriticalSection {
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unsafe fn acquire() -> critical_section::RawRestoreState {
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let mut mstatus = 0u32;
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core::arch::asm!("csrrci {0}, mstatus, 8", inout(reg) mstatus);
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let interrupts_active = (mstatus & 0b1000) != 0;
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interrupts_active as _
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}
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unsafe fn release(token: critical_section::RawRestoreState) {
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if token != 0 {
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riscv::interrupt::enable();
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}
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}
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}
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}
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