0aa0232f1b
* Duplicate spi to spi_slave * Restore spi * Add barebones SPI slave mode, DMA only. This setup allows registering buffers for future transactions the master does (lowering cs, toggling sclk, and raising cs again). The transfer struct returned from the registration API will complete its wait() or return true from is_done() after cs has been raised. Copied from spi.rs, so most of the changes are deleting code that handles e.g. segmented transfers or synchronous operations. Fix non-c3 devices' builds * Limit spi_slave to non-pdma devices * SPI slave DMA example Ensure the API "feels" right. Since there's no way to route GPIOs to other peripherals, we choose four other wires and bit-bang SPI for the master side, relying on the person running the example to connect the bus. This way we ensure the slave code works, since we created the master ourselves. Also, it's not really possible to use a second ESP device as the master anyway: all the digital lines have glitches on startup, and those glitches cause the slave's DMA engine to skip descriptors (it thinks they're intended CS indicators); this causes it to lose data. Then, fix the bitbang master (recording the progression here) - When bitbanging, iterate the bits by "for _ in 0..8", instead of the broken "for _ in [0..8]". The latter only runs the iteration once, since there's only one list given ... and because the code uses _ instead of a real loop variable, type checking didn't save us. - When bitbanging, send the bits out (and read them in) MSB first, since that's actually how we have the slave configured. * Add changelog entry * Split DMA prepare_transfer into two fns. The first does everything but write to the start bit and check for an error. The second does those. We need 2 fns because the SPI slave needs to start the transfer only after resetting the various afifo hardware components (if it starts the transfer before, the first 8 bytes will be lost when that reset happens). Use the split fns everywhere. Also split flush(). It needs to be pollable, so split it into one fn that polls and one that waits until the poll returns clear. Also call the poll fn from the is_done() fn, so we don't trample in-progress transfers. * Make example code fill rx buffer before transfer This way we can tell if it's ever touching certain bytes - 0xff is never added to the master transmit buffer. While I'm changing this, make the slave tx buffer never contain 0xff either (go from 254 to 0). --------- Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com> |
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| README.md | ||
esp32c2-hal
no_std HAL for the ESP32-C2 from Espressif.
Implements a number of the traits defined in embedded-hal.
This device uses the RISC-V ISA, which is officially supported by the Rust compiler via the riscv32imc-unknown-none-elf target.
Please refer to the documentation for more information.
Documentation
Resources
- Datasheet
- Technical Reference Manual
- The Rust Programming Language
- The Embedded Rust Book
- The Rust on ESP Book
Getting Started
Installing the Rust Compiler Target
The compilation target for this device is officially supported by the mainline Rust compiler and can be installed using rustup:
rustup target add riscv32imc-unknown-none-elf
License
Licensed under either of:
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.