848029b152
* Mark interconnect as unstable * Explicitly set unstable feature in HIL tests * WIP append feature set name to artifact * Add name to feature sets, build all combinations * Fix tests * Provide a looping executor for stable async tests * Fix usb serial jtag * Hide interconnect types
46 lines
1.2 KiB
Rust
46 lines
1.2 KiB
Rust
//! Misc UART TX/RX regression tests
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: unstable
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#![no_std]
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#![no_main]
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3)]
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mod tests {
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use esp_hal::{
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gpio::OutputPin,
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uart::{self, UartRx, UartTx},
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};
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use hil_test as _;
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use nb::block;
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#[test]
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fn test_that_creating_tx_does_not_cause_a_pulse() {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (rx, mut tx) = hil_test::common_test_pins!(peripherals);
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let mut rx = UartRx::new(peripherals.UART1, uart::Config::default())
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.unwrap()
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.with_rx(rx);
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// start reception
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_ = rx.read_byte(); // this will just return WouldBlock
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unsafe { tx.set_output_high(false, esp_hal::Internal::conjure()) };
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// set up TX and send a byte
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let mut tx = UartTx::new(peripherals.UART0, uart::Config::default())
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.unwrap()
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.with_tx(tx);
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tx.flush().unwrap();
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tx.write_bytes(&[0x42]).unwrap();
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let read = block!(rx.read_byte());
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assert_eq!(read, Ok(0x42));
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}
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}
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