[package]
name         = "esp-riscv-rt"
version      = "0.6.0"
edition      = "2021"
rust-version = "1.65"
description  = "Minimal runtime / startup for RISC-V CPUs from Espressif"
repository   = "https://github.com/esp-rs/esp-hal"
license      = "MIT OR Apache-2.0"
keywords     = ["esp32", "riscv", "runtime", "startup"]
categories   = ["embedded", "no-std"]

[dependencies]
riscv           = "0.10.1"
riscv-rt-macros = "0.2.0"

[features]
direct-vectoring     = []
fix-sp               = []
has-mie-mip          = []
init-data            = []
init-rtc-fast-data   = []
init-rtc-fast-text   = []
init-rw-text         = []
interrupt-preemption = []
zero-bss             = []
zero-rtc-fast-bss    = []

# This feature is intended for testing; you probably don't want to enable it:
ci = [
    "direct-vectoring",
    "fix-sp",
    "has-mie-mip",
    "init-data",
    "init-rtc-fast-data",
    "init-rtc-fast-text",
    "init-rw-text",
    "interrupt-preemption",
    "zero-bss",
    "zero-rtc-fast-bss",
]