# NOTE: # # When adding support for a new chip to `esp-hal`, there are a number of # updates which must be made to the CI workflow in order to reflect this; the # changes are: # # 1.) In the 'esp-hal' job, add the name of the chip to the `matrix.soc` array. # 1a.) If the device has a low-power core (which is supported in # `esp-lp-hal`), then update the `if` condition to build prerequisites. # 2.) In the 'msrv-riscv' job, add checks as needed for the new chip. # 3.) In the 'clippy-riscv' job, add checks as needed for the new chip. # 3.) In the 'rustfmt' job, add checks as needed for the new chip. name: CI on: pull_request: paths-ignore: - "**/CHANGELOG.md" - "**/README.md" - "**/hil-test/**" push: branches-ignore: - "gh-readonly-queue/**" paths-ignore: - "**/CHANGELOG.md" - "**/README.md" - "**/hil-test/**" merge_group: workflow_dispatch: env: CARGO_TERM_COLOR: always GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} MSRV: "1.76.0" # Cancel any currently running workflows from the same PR, branch, or # tag when a new workflow is triggered. # # https://stackoverflow.com/a/66336834 concurrency: cancel-in-progress: true group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} jobs: # -------------------------------------------------------------------------- # Build Packages esp-hal: runs-on: ubuntu-latest strategy: fail-fast: false matrix: soc: [ # RISC-V devices: "esp32c2", "esp32c3", "esp32c6", "esp32h2", # "esp32p4", # Xtensa devices: "esp32", "esp32s2", "esp32s3", ] steps: - uses: actions/checkout@v4 # Install the Rust toolchain for RISC-V devices: - if: ${{ !contains(fromJson('["esp32", "esp32s2", "esp32s3"]'), matrix.soc) }} uses: dtolnay/rust-toolchain@v1 with: target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf toolchain: nightly components: rust-src # Install the Rust toolchain for Xtensa devices: - if: contains(fromJson('["esp32", "esp32s2", "esp32s3"]'), matrix.soc) uses: esp-rs/xtensa-toolchain@v1.5 with: buildtargets: ${{ matrix.soc }} default: true ldproxy: false - uses: Swatinem/rust-cache@v2 # Build all supported examples for the low-power core first (if present): - if: contains(fromJson('["esp32c6", "esp32s2", "esp32s3"]'), matrix.soc) name: Build prerequisites (esp-lp-hal) run: cargo xtask build-examples esp-lp-hal ${{ matrix.soc }} # Build all supported examples for the specified device: - name: Build examples run: cargo xtask build-examples esp-hal ${{ matrix.soc }} # Ensure we can build the documentation for the specified device: - name: Build documentation run: cargo xtask build-documentation esp-hal ${{ matrix.soc }} esp-lp-hal: runs-on: ubuntu-latest strategy: fail-fast: false matrix: soc: ["esp32c6", "esp32s2", "esp32s3"] steps: - uses: actions/checkout@v4 # Install the Rust toolchain for RISC-V devices: - uses: dtolnay/rust-toolchain@v1 with: target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf toolchain: nightly components: rust-src - uses: Swatinem/rust-cache@v2 # Build all supported examples for the specified device: - name: Build examples run: cargo xtask build-examples esp-lp-hal ${{ matrix.soc }} # Ensure we can build the documentation for the specified device: - name: Build documentation run: cargo xtask build-documentation esp-lp-hal ${{ matrix.soc }} esp-riscv-rt: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@v1 with: target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf toolchain: nightly components: rust-src - uses: Swatinem/rust-cache@v2 # Build for all RISC-V targets (no features): - name: Build esp-riscv-rt (riscv32imc, no features) run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf - name: Build esp-riscv-rt (riscv32imac, no features) run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf - name: Build esp-riscv-rt (riscv32imafc, no features) run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imafc-unknown-none-elf # Build for all RISC-V targets (all features): - name: Build esp-riscv-rt (riscv32imc, all features) run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf --features=ci - name: Build esp-riscv-rt (riscv32imac, all features) run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf --features=ci - name: Build esp-riscv-rt (riscv32imafc, all features) run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imafc-unknown-none-elf --features=ci # Ensure documentation can be built - name: rustdoc run: cd esp-riscv-rt/ && cargo doc # -------------------------------------------------------------------------- # MSRV msrv-riscv: runs-on: ubuntu-latest env: RUSTC_BOOTSTRAP: 1 steps: - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@v1 with: target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf toolchain: ${{ env.MSRV }} components: rust-src - uses: Swatinem/rust-cache@v2 # TODO: # - Enable additional (all?) features for MSRV check # Verify the MSRV for all RISC-V chips. - name: msrv (esp-hal) run: | cargo xtask build-package --features=esp32c2 --target=riscv32imc-unknown-none-elf esp-hal cargo xtask build-package --features=esp32c3 --target=riscv32imc-unknown-none-elf esp-hal cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf esp-hal cargo xtask build-package --features=esp32h2 --target=riscv32imac-unknown-none-elf esp-hal # cargo xtask build-package --features=esp32p4 --target=riscv32imafc-unknown-none-elf esp-hal - name: msrv (esp-lp-hal) run: | cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf esp-lp-hal cargo xtask build-package --features=esp32s2 --target=riscv32imc-unknown-none-elf esp-lp-hal cargo xtask build-package --features=esp32s3 --target=riscv32imc-unknown-none-elf esp-lp-hal msrv-xtensa: runs-on: ubuntu-latest env: RUSTC_BOOTSTRAP: 1 # TODO: # - Enable additional (all?) features for MSRV check steps: - uses: actions/checkout@v4 - uses: esp-rs/xtensa-toolchain@v1.5 with: ldproxy: false version: ${{ env.MSRV }} - uses: Swatinem/rust-cache@v2 # Verify the MSRV for all Xtensa chips: - name: msrv (esp-hal) run: | cargo xtask build-package --toolchain=esp --features=esp32 --target=xtensa-esp32-none-elf esp-hal cargo xtask build-package --toolchain=esp --features=esp32s2 --target=xtensa-esp32s2-none-elf esp-hal cargo xtask build-package --toolchain=esp --features=esp32s3 --target=xtensa-esp32s3-none-elf esp-hal # -------------------------------------------------------------------------- # Lint clippy-riscv: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@v1 with: toolchain: nightly targets: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf components: clippy,rust-src - uses: Swatinem/rust-cache@v2 # Run 'cargo clippy' on all packages targeting RISC-V: ## esp-hal: - name: clippy (esp-hal, esp32c2) run: cd esp-hal && cargo clippy --features=esp32c2 --target=riscv32imc-unknown-none-elf -- -D warnings - name: clippy (esp-hal, esp32c3) run: cd esp-hal && cargo clippy --features=esp32c3 --target=riscv32imc-unknown-none-elf -- -D warnings - name: clippy (esp-hal, esp32c6) run: cd esp-hal && cargo clippy --features=esp32c6 --target=riscv32imac-unknown-none-elf -- -D warnings - name: clippy (esp-hal, esp32h2) run: cd esp-hal && cargo clippy --features=esp32h2 --target=riscv32imac-unknown-none-elf -- -D warnings # TODO: Re-enable when able # - name: clippy (esp-hal, esp32p4) # run: cd esp-hal && cargo clippy --features=esp32p4 --target=riscv32imafc-unknown-none-elf -- -D warnings ## esp-hal-smartled: - name: clippy (esp-hal-smartled) run: cd esp-hal-smartled && cargo clippy --features=esp32c6 --target=riscv32imac-unknown-none-elf -- -D warnings ## esp-lp-hal: - name: clippy (esp-lp-hal, esp32c6) run: cd esp-lp-hal && cargo clippy --features=esp32c6 --target=riscv32imac-unknown-none-elf -- -D warnings - name: clippy (esp-lp-hal, esp32s2) run: cd esp-lp-hal && cargo clippy --features=esp32s2 --target=riscv32imc-unknown-none-elf -- -D warnings - name: clippy (esp-lp-hal, esp32s3) run: cd esp-lp-hal && cargo clippy --features=esp32s3 --target=riscv32imc-unknown-none-elf -- -D warnings # esp-riscv-rt: - name: clippy (esp-riscv-rt) run: cd esp-riscv-rt && cargo clippy --target=riscv32imc-unknown-none-elf -- -D warnings clippy-xtensa: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - uses: esp-rs/xtensa-toolchain@v1.5 with: default: true ldproxy: false - uses: Swatinem/rust-cache@v2 # Run 'cargo clippy' on all packages targeting Xtensa: - name: clippy (esp-hal, esp32) run: cd esp-hal && cargo clippy -Zbuild-std=core --features=esp32 --target=xtensa-esp32-none-elf -- -D warnings - name: clippy (esp-hal, esp32s2) run: cd esp-hal && cargo clippy -Zbuild-std=core --features=esp32s2 --target=xtensa-esp32s2-none-elf -- -D warnings - name: clippy (esp-hal, esp32s3) run: cd esp-hal && cargo clippy -Zbuild-std=core --features=esp32s3 --target=xtensa-esp32s3-none-elf -- -D warnings rustfmt: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 # Some of the configuration items in 'rustfmt.toml' require the 'nightly' # release channel: - uses: dtolnay/rust-toolchain@v1 with: toolchain: nightly components: rustfmt - uses: Swatinem/rust-cache@v2 # Check the formatting of all packages: - name: rustfmt (esp-hal) run: cargo fmt --all --manifest-path=esp-hal/Cargo.toml -- --check - name: rustfmt (esp-hal-procmacros) run: cargo fmt --all --manifest-path=esp-hal-procmacros/Cargo.toml -- --check - name: rustfmt (esp-hal-smartled) run: cargo fmt --all --manifest-path=esp-hal-smartled/Cargo.toml -- --check - name: rustfmt (esp-lp-hal) run: cargo fmt --all --manifest-path=esp-lp-hal/Cargo.toml -- --check - name: rustfmt (esp-riscv-rt) run: cargo fmt --all --manifest-path=esp-riscv-rt/Cargo.toml -- --check - name: rustfmt (examples) run: cargo fmt --all --manifest-path=examples/Cargo.toml -- --check # -------------------------------------------------------------------------- # NOTE: # # This is (hopefully) a temporary workaround to allow us to run HIL tests # in merge queue, but not in pull requests. For more information see: # # https://github.com/esp-rs/esp-hal/issues/1328 riscv-hil: name: HIL Test | ${{ matrix.soc }} runs-on: ubuntu-latest strategy: fail-fast: false matrix: soc: [esp32c3, esp32c6, esp32h2] steps: - run: echo "HIL tests are not run in pull requests!"