[package]
name         = "esp-riscv-rt"
version      = "0.6.1"
edition      = "2021"
rust-version = "1.65"
description  = "Minimal runtime / startup for RISC-V CPUs from Espressif"
repository   = "https://github.com/esp-rs/esp-hal"
license      = "MIT OR Apache-2.0"
keywords     = ["esp32", "riscv", "runtime", "startup"]
categories   = ["embedded", "no-std"]

[dependencies]
document-features = "0.2.7"
riscv             = "0.11.0"
riscv-rt-macros   = "0.2.1"

[features]
## Move the stack to the start of RAM to get zero-cost stack overflow
## protection (ESP32-C6 and ESP32-H2 only!)
fix-sp = []
## Indicate that the device supports `mie` and `mip` instructions.
has-mie-mip = []

#! ### Memory Initialization Feature Flags
## Initialize the `data` section.
init-data = []
## Initialize the `.rtc_fast.data` section.
init-rtc-fast-data = []
## Initialize the `.rtc_fast.text` section.
init-rtc-fast-text = []
## Initialize the `.rwtext` section.
init-rw-text = []
## Zero the `.bss` section.
zero-bss = []
## Zero the `.rtc_fast.bss` section.
zero-rtc-fast-bss = []

#! ### Interrupt Feature Flags
## Enable direct interrupt vectoring.
direct-vectoring = []
## Enable interrupt preemption.
interrupt-preemption = []

# This feature is intended for testing; you probably don't want to enable it:
ci = [
    "direct-vectoring",
    "fix-sp",
    "has-mie-mip",
    "init-data",
    "init-rtc-fast-data",
    "init-rtc-fast-text",
    "init-rw-text",
    "interrupt-preemption",
    "zero-bss",
    "zero-rtc-fast-bss",
]