* Fix Async UART
The uart handler was `writing` to the enable register instead of
`modify`, which meant any wake would see the cleared enabled bit and
think the event had occurred. This wasn't seen before the split of uart
because it was only possible to listen to one thing at a time.
This PR also removes the ReadBufferFull error in favour of returning the
max bytes in the buffer.
The serial examples has been updated to actually have some cross task
communication.
* changelog
* fix dev deps
* RISCV interrupt vectoring
- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes
* remove .vscode files
* Support vectored edge interrupts
This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.
* fix all examples to use vectoring
* doc & cleanup
* run handlers from ram
* make xtensa::interrupt::vectored private, we rexport public items
* fix default handlers
* pass interrupt into EspDefaultHandler
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
* make esp32c3 examples run from flash / flashable
* use gpio3 for blinky
* direct boot in Cargo.toml
* have a shared gpio impl
* use PACs from their original locations again
