* H2: Add initial i2s support and i2s_read and i2s_sound examples
* Add I2S_SCLK and I2S_DEFAULT_CLK_SRC constants for all chips
* Update I2S driver
* fmt
* Add changelog
* Change DIN GPIO17 to GPIO14 in ESP32 i2s_read example
* First README prototype
* README update
Fixed link, uncommented Matrix link, made some preparations before docs will be posted
* Added a change to CHANGELOG
* typo: return header sign back
* Process Fosc frequencies for ECO1+ ESP32C6 chips
e3148369f3
* Final update for FOSC calibration (ESP32C6)
+ fixed few errors
* Fix format + add update to Changelog
Formatting
Formatting (1)
* H2: Use PLL_48M_CLK in Timg driver and add imer_interrupt example
* Clean timer driver, add helper configure_src_clk and configure_wdt_src_clk methods
* H2: Add imer_interrupt example
* add helper methods for selecting default clk src
* Change PR number in the Changelog
* Add efuse field tables from IDF
* Add efuse fields constants generator
* Fix MAC field in efuse tables
* Add common efuse field impl
* Add efuse fields support for chips
* Add efuse changes to changelog
* Async GPIO multibank fix
- Removes dead code from the default impl of the BankAccess trait
- Adds one new function to the async module to control the interrupt
enable for any pin
* Add changelog entry
* Simplify the `Delay` driver, derive `Clone` and `Copy`
The RISC-V and Xtensa implementations of the delay functionality are both safe to access from multiple contexts, and the `Delay` struct does not take ownership of any peripheral struct, so `Delay` is safe to clone/copy
* Update the CHANGELOG
* Update the `GDMA` driver to support the ESP32-H2
* Update the `SPI` driver to support the ESP32-H2
* Add `SPI` examples for ESP32-H2
* Update CHANGELOG
* Remove copy-pasted references to ESP32-C6
* Update GPIO pins used in SPI examples, add `qspi_flash` example
* Update SPI clock configuration to produce correct clock rate
* Correct comment regarding clock source frequency
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
* H2: Add PLL_48M_CLK src to ClockControl and RawClocks
* H2: Use PLL_48M_CLK as SPI clk src
* H2: cleanup commented block in SPI driver
* H2: update docs comment in embassy_spi example
* fmt
* Add a new line in embassy_spi example
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
* Support for multicore async GPIO:
Use the correct registers depending on which core the interrupt is being
serviced on. Fixed a bug in the `esp32::gpio_intr` which would enable
the interrupt on both cores. It now enables the interrupt for the core
in which `listen()` is called.
* add changelog item
* Simplify GPIO interrupt status
For now, only the -c3.
---
Open up LEDC fade support to all chips.
The C6 chip needs some special handling because its fade registers also
handle gamma, and the ESP chip needs some special handling because it
has two banks of channels. The code to handle these is already present
in channel.rs, but needs to be copied and adapted. Do that, and drop
all the esp32c3 feature checks.
---
Add a function to poll the duty-fade state
Use the unmasked interrupt bit in the LEDC register block, since that
will get updated by the hardware whether or not we've connected anything
to the interrupt source. Also be sure to clear that bit before starting
a new fade, so it's always clear while fading.
This will allow dumb (non-async-code) polling of the fade state after
one is started by the start_duty_fade API.
---
Fix non-C3 devices to use the right int_raw bits
These are inconsistently named between the esp32 variants.
---
Add examples of hardware duty-cycle fading
Just a relatively simple zero to 100 and back to zero, over a total of 2
seconds, to get a breathing effect.
This does make the main loop{} have a 2-second period instead of the
current nearly-zero period, but nothing else is happening so that's
fine.
---
Fix two bugs in hardware fading
When figuring out how many duty-cycle changes need to happen per counter
overflow, we need to use the absolute value of the difference between
the start and end duty values, not the raw difference. When fading from
(e.g.) 100% to 0, this will overflow, and both the debug-mode panic and
the release-mode wrapping behavior give the wrong delta value.
So calculate an absolute value difference first, and use that.
Then, when running through the while loop that allocates bits between
pwm_cycles and duty_cycle, the check on pwm_cycles was wrong -- since
the value reduces each time through the loop, we need to keep looping as
long as it's *above* some threshold, not below.
---
Simplify and refactor duty-cycle fade code
I'm not sure if this will fix the extremely-short fade times that we're
seeing with the older code, but we'll see.
Move all the calculations out of the ChannelHW implementations, and make
those *just* set registers. The calculations are the same for all chip
variants, so don't need to be duplicated for each chip feature, like the
register macros are.
Change the calculations from a loop doing bit shifts, to an explicit
division and a couple of range checks. This way we can get a lot closer
to the requested percentages and durations.
Use the u32::abs_diff function instead of open-coding it (now that I see
it exists).
Use u16::try_from() to limit the range of values, and use try_into<u16>
and map_err and the ? operator to more clearly handle numbers out of
range.
Drop the Result<> return type from the ChannelHW function, as it can't
fail anymore.
Fix the duty_range value -- before, when duty_exp was (say) 8,
duty_range would be 256, and if one of the *_duty_pct values was 100,
the start or end duty value would be too big. The range of start and
end duty values is 0..255, so we have to subtract one to handle 100%.
Finally, add a comment on the is_duty_fade_running{,_hw} methods.
---
Some fades can't work; return errors for them.
Add a new Error enum value with a sub-error enum with more details.
Return it from the error cases in the fade method.
If the calculated cycles_per_step is more than 10 bits, fail as well;
the field in the register is only 10 bits wide.
Fix all the examples to run a 1-second fade instead of a 2-second, since
the 2-second fade will run into this error. (Assert that, as well.)
---
When fading on a -c6 chip, set two more registers
The gamma functionality of -c6 chips needs two more fields set. One
tells the chip how many gamma stages it should iterate through, but we
only implement linear fading, so always use 1. The other tells the chip
to latch the value of the other gamma registers into the chosen slot, so
even though its value never changes, the write needs to happen.
---
Add changelog entry
* async gpio fixes
- Fix pin number calculation for bank1
- Clear interrupt status after disabling interrupt to avoid hardware
pending another interrupt
- Clear interrupt status per pin when we create the input future
* add changelog item
* Small refactor to extract functions for setting up reads/writes
* Implement async capabilities for `I2C` driver
* Add async I2C examples for each supported chip
* Update CHANGELOG
Once the timer has been initialized, all other operations are atomic.
Therefore we can simply `steal` the timer where needed, instead of
holding it in a mutex/refcell.
* Added init function
* Populated enums
* Adding enums
* Add TODO (according to IDF update)
* Added WDT support for ESP32-H2
* Updated hello_world example
* Add two examples for both watchdog and RTC watchdog
* Add specific bit initialization for TIMG0 and TIMG1
* Cleaning the code
* adjusting for rustfmt
* uncommented direct-boot feature test in CI
* Begin working on `PeripheralClockControl` for the ESP32-H2
* Update `UART` driver to add H2 support
* Update `TIMG` driver to add H2 support
* Update the hello_world example to use `TIMG` and `UART`
* implement fetching the rtc timer value in miliseconds and mircroseconds
* fmt cleanup
* add rtc_time examples
* get_time_raw/esp32: delay 1us between time update checks like esp-idf
* cargo fmt
* Initial async_{write|flush} implementations
- ESP32C3 + UART0 example
* Support UART1 & UART2
* Add examples for all chips
* reduce number of wakers depending on uart count
* Software interrupt support added, not sure if the code is good
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* prio based preemption only, vector table reverted
* prio based preemption only, vector table reverted
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed rare bug causing misaligned memory access when emulating atomics
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* broke something
* broke something
* fixed alignment bug
* Tentative: added support for interrupt preemption without involving the rt
* Added feature enabling priority based interrupt preemption
* Fixed failed merge
* Tagged preemption helpers with inline always
* Disable interrupts before restoring context to avoid ruining it
* Fix max priority edge case
* Fix broken merge
* Added examples for the remaining RISC-V ESPs
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp32c2-hal/examples/interrupt_preemption.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Example comments courtesy of @sethp
* Reverted irrelevant changes, raised high prio interrupt to max prio
* Rolling back an irrelevant change
* Rolling back an irrelevant change
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Moved imports to avoid warnings, moved functions to ram, moved interrupt disable to before prio threshold is restored
* Added preemption for the ESP32C6
* Moved helper functions into the relevant modules, changed threshold for ESP32C6 to machine mode one
* ESP32C6 Threshold register changed to machine mode one, corrected threshold set.
---------
Co-authored-by: sethp <seth.pellegrino@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update `embedded-hal-1` and `embedded-hal-nb` dependencies to latest versions
* Update the `Delay` and `I2c` trait implementations
* Update the `SpiDevice` trait, implement `SpiDeviceRead` and `SpiDeviceWrite`
* Add README, improve documentation for `esp-hal-procmacros`
* Improve documentation for `esp-hal-smartled`
* Use esp-rs logo for all packages' documentation
* esp32 & esp32s2 sharing scripts
* add wokwi files
* Add fixup section for esp32s2, fix ordering of sectino includes
* Remove debug asm file
* Use shared linker scripts for s3 with fixups
* Add external.x sections back
* Move ld scripts into esp-hal-common
* esp32c3 unified linker scripts
- rework original c3 script to use the xtensa named sections
(e.g, _SECTIONNAME_start)
- Add fixups in esp32c3 specific linker
- Remove useless text section start and end (not required when using any
form of bootloader)
* Add RTC alias'. Move some shared fixups to a file
* comment and cleanup
* unify c2 linker script
* unify c6 linker script
* remove debug configs
* use new esp-riscv-rt
* fmt
* align db symbol names
* fix s3 db
* Add additional `cfg` gates to re-exports in `esp-hal-common`
This leaves only `clock`, `delay`, `peripheral`, `prelude`, `rom`, and `soc` *not* behind `cfg`s
* Simplify the prelude, update its `cfg`s, and re-export some missing traits
* Update various dependencies
* Extract the `esp-hal-smartled` package
This (finally) eliminates the `esp_hal_common::utils` module!
* Remove all references to the old `smartled` feature from CI
* RISCV: Separate PLIC and non-PLIC
* De-duplicate code
* Write 0 to INTR_MAP again to disable peripheral interrupts
* Limit visibility of `get_assigned_cpu_interrupt`
* Move some linker scripts into `esp-hal-common` and update the build script
* Move `EspDefaultHandler` and `DefaultHandler` definitions into `esp-hal-common`
* Re-export everything from `esp-hal-common`
* Add a couple cfg symbols, cleanup/organize some exports/modules
* Create an `soc` module with a submodule for each chip, move `peripherals` in
* Move the `cpu_control` module into `soc`
* Move the `efuse` module into `soc`
* Refactor type definitions from `gpio` module into `soc`
* Put all embassy-related files in a common directory
* Change visibility of `GpioPin` constructor
