Commit Graph

5 Commits

Author SHA1 Message Date
Jordan Halase
f22cd7370d
Add CRC functionality from ESP ROM (#587)
* Add ESP ROM CRC and fallbacks to HAL

* Cargo fmt

* Add CRC examples

* Cargo fmt

* Cargo fmt and clippy (all)

* Update CHANGELOG.md
2023-06-14 05:40:51 -07:00
bjoernQ
3dabd57a1d Fix ESP32-H2 direct-boot 2023-05-31 08:39:39 -07:00
Jesse Braham
d86300f799
Add all SPI examples for the ESP32-H2 (#549)
* Update the `GDMA` driver to support the ESP32-H2

* Update the `SPI` driver to support the ESP32-H2

* Add `SPI` examples for ESP32-H2

* Update CHANGELOG

* Remove copy-pasted references to ESP32-C6

* Update GPIO pins used in SPI examples, add `qspi_flash` example

* Update SPI clock configuration to produce correct clock rate

* Correct comment regarding clock source frequency

Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>

* H2: Add PLL_48M_CLK src to ClockControl and RawClocks

* H2: Use PLL_48M_CLK as SPI clk src

* H2: cleanup commented block in SPI driver

* H2: update docs comment in embassy_spi example

* fmt

* Add a new line in embassy_spi example

---------

Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
2023-05-31 09:49:13 +02:00
sethp
171e66e87a
feat(riscv): relocate .trap machinery to RAM (#541)
* feat: relocate riscv isr to iram

Previously, the trap vector itself and its immediate callees
(`_start_trap` and `_start_trap_rust_hal`) were located in the mapped
instruction flash range `0x420..`, increasing cache pressure and adding
variable latency to the very beginning of the interrupt/exception
service flow.

This change places those routines in iram directly:

```
   Num:    Value  Size Type    Bind   Vis      Ndx Name
 48177: 40380280  2428 FUNC    GLOBAL DEFAULT    6 _start_trap_rust_hal
 48197: 40380bfc    54 FUNC    GLOBAL DEFAULT    6 _start_trap_rust
 48265: 40380200     0 FUNC    GLOBAL DEFAULT    6 _vector_table
 48349: 40380100     0 NOTYPE  GLOBAL DEFAULT    6 default_start_trap
 48350: 40380100     0 NOTYPE  GLOBAL DEFAULT    6 _start_trap
```

As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx`

* feat(riscv): place .trap in RAM

This change follows through on relocating the `_vector_table`,
`_start_trap`, and `_start_trap_rust` functions for all present
build/link modes for the 'c2, 'c3, 'c6, and 'h2.

It has been tested by running the `software_interrupts` example for the
'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to
identify how to run the `mcu-boot` mode for the 'c3, nor do I have
present access to any of the other devices for testing.

* docs: Update CHANGELOG.md
2023-05-26 20:48:49 +01:00
Kirill Mikhailov
9493b38a1b Started adding ESP32-H2 support (#482) 2023-05-08 08:03:08 -07:00