Commit Graph

13 Commits

Author SHA1 Message Date
bjoernQ
a4bc624e2d Fix ESP32-S3 PSRAM start address calculation 2023-07-04 11:47:21 +01:00
Jesse Braham
c32e9fdab0 Fix some warnings relating to ADC and eFuse 2023-06-20 07:43:31 -07:00
Juraj Sadel
3b689b2a52
H2: Add I2S support (#597)
* H2: Add initial i2s support and i2s_read and i2s_sound examples

* Add I2S_SCLK and I2S_DEFAULT_CLK_SRC constants for all chips

* Update I2S driver

* fmt

* Add changelog

* Change DIN GPIO17 to GPIO14 in ESP32 i2s_read example
2023-06-19 06:24:09 -07:00
Kayo Phoenix
c6bdf8b8c0
Unified efuse field access (#567)
* Add efuse field tables from IDF

* Add efuse fields constants generator

* Fix MAC field in efuse tables

* Add common efuse field impl

* Add efuse fields support for chips

* Add efuse changes to changelog
2023-06-05 06:15:00 -07:00
Dániel Buga
02c7e38cf5
Remove a bunch of generic params from GpioPin (#553) 2023-05-22 12:27:36 +01:00
Scott Mabin
45f855abf5
Support for multicore async GPIO: (#542)
* Support for multicore async GPIO:

Use the correct registers depending on which core the interrupt is being
serviced on. Fixed a bug in the `esp32::gpio_intr` which would enable
the interrupt on both cores. It now enables the interrupt for the core
in which `listen()` is called.

* add changelog item

* Simplify GPIO interrupt status
2023-05-16 15:46:36 +01:00
bjoernQ
7f769612b9 Set vecbase on core1 2023-05-15 16:09:43 +02:00
Björn Quentin
13acedf69a
ESP32: Initial PSRAM Support (#506)
* ESP32: Initial PSRAM Support

* Update CHANGELOG, fmt
2023-05-04 12:21:24 +01:00
dimpolo
8815e75250
fix CpuControl::start_app_core signature (#466) 2023-04-05 16:37:22 +01:00
bjoernQ
4bd05d9032 Fix typo 2023-03-27 13:01:36 +02:00
bjoernQ
94bbdac00e Add support for radio peripheral clock control 2023-03-27 10:26:45 +02:00
Jesse Braham
a0b72bdfa5 Use latest PACs and make required changes 2023-03-14 06:23:58 -07:00
Jesse Braham
984b7fc042
Refactor chip-specific code into esp_hal_common::soc module (#412)
* Create an `soc` module with a submodule for each chip, move `peripherals` in

* Move the `cpu_control` module into `soc`

* Move the `efuse` module into `soc`

* Refactor type definitions from `gpio` module into `soc`

* Put all embassy-related files in a common directory

* Change visibility of `GpioPin` constructor
2023-02-28 07:49:41 -08:00