GetLitFam/esp-hal
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15 Commits

Author SHA1 Message Date
W Etheredge
a2883ac318
Take 2 on #[ram] soundness (#1677) 
* Improve `#[ram]` soundness

* Allow `Atomic*` in `#[ram(persistent)]`

---------

Co-authored-by: Scott Mabin <scott@mabez.dev>
 2024-07-10 13:30:48 +00:00
Scott Mabin
25f509ce74
discard interrupt symbols from lto so that lto doesn't end up rebinding them (#1327) 2024-03-21 15:38:07 +00:00
Scott Mabin
1444b62777
ensure we don't strongly define cpu int handlers (#1324) 2024-03-21 13:46:49 +00:00
Scott Mabin
a61ffef909
RISCV: remove the direct-vectoring & interrupt-preemption features and enable them by default (#1310) 
* Remove the `direct-vectoring` feature

* Enables the feature by default
* renames the old direct_vectoring enable function `enable_direct`

* Make enable_direct safe, move it out of vectored module

* enable interrupt preemption by default for riscv

* remove pub from cpu intr handlers

* add enable_direct for Xtensa too

* Fix flip-link feature

* Fix up interrupt docs

* changelog

* fix clippy suggestions

* Disable P4 workflow
 2024-03-20 16:19:22 +00:00
Jesse Braham
ac07f3c460
Document the features of the remaining packages (#1143) 
* Document features for `esp-riscv-rt` package

* Document features for `esp-hal-smartled`

* Document features for `esp-hal-procmacros`
 2024-02-06 07:12:05 -08:00
Björn Quentin
c0f9169879
Support Rust's stack-protector feature (#1135) 
* Support Rust's `stack-protector` feature

* Update changelogs
 2024-02-02 13:56:39 +00:00
Scott Mabin
4ea4a809fd Document msrv toolchain per chip hal 2024-01-17 15:30:48 +00:00
Björn Quentin
c1912fc079
C6/H2: flip-link feature (#1008) 
* C6/H2: flip-link feature

* CHANGELOG.md entry

* Include .wifiextrairam in .rwtext.wifi

* Set exception code 14 if SP was out of bounds
 2023-12-11 12:45:07 +00:00
Björn Quentin
a40ea79277
Fix RISC-V stack allocation (#988) 2023-12-01 09:17:00 +00:00
Björn Quentin
8c5fda2d53
Fix zero/copy data in esp-riscv-rt (#952) 
* Fix zero/copy data in esp-riscv-rt

* CHANGELOG.md
 2023-11-17 10:49:40 +00:00
Jesse Braham
c63f40f412
Actually enforce clippy lints in CI (#767) 
* Actually enforce clippy lints in CI

* Fix a couple clippy lints in `esp-riscv-rt`

* Fix a couple clippy lints for `esp32c6-lp-hal`
 2023-08-30 10:30:36 -07:00
Björn Quentin
424b96532f
Fix RISCV stack-start (#721) 2023-08-14 17:05:29 +02:00
Björn Quentin
92bda00296
Remove heap related symbols, use all remaining memory for the stack (#716) 
* Use all remaining memory for stack(s)

* Remove HEAP related code from RISCV linker scripts

* Fix direct-boot / mcu-boot linker scripts

* Use a statically allocated stack for core-1
 2023-08-14 13:38:36 +02:00
onsdagens
d6d5e0c86b
Adding direct vector table hooking support for RISC-V's (#621) 
* direct vectoring support added

* provide minimal handlers for hooking the vector table directly

* changed direct vectoring interrupt enable interface to map to CPU interrupt

* direct vectoring interrupt nesting

* removed unused dependency

* added tentative c2 and c6 support for direct vector table hooking

* added direct vectoring examples

* added direct vectoring examples

* updated changelog

* added direct vectoring to CI

* Added H2 support and example, moved helpers to esp-hal-common

* Added H2 direct vectoring example to CI

* Removed remnants of removed feature

* C6 and H2 examples fixed

* C6 and H2 examples fixed

* C6 and H2 examples fixed

* Comment fixed

* Added preemption flag to RT

---------

Co-authored-by: Scott Mabin <scott@mabez.dev>
 2023-08-01 16:28:40 +01:00
Scott Mabin
8361ca308c
Move esp-riscv-rt into esp-hal (#578) 
* Move esp-riscv-rt into esp-hal

* Add changelog entry
 2023-06-07 08:15:47 -07:00