* Create issue_handler.yml
* No longer re-export `embedded-hal`, hide exported macros in documentation
* Add simple package-level documentation for each HAL package
* Clean up/simplify re-exports
* Fix the examples that I broke
* Ensure top-level modules/types/functions have doc comments
* Update CHANGELOG
* Re-export the `soc::psram` module where available
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
* H2: Add initial i2s support and i2s_read and i2s_sound examples
* Add I2S_SCLK and I2S_DEFAULT_CLK_SRC constants for all chips
* Update I2S driver
* fmt
* Add changelog
* Change DIN GPIO17 to GPIO14 in ESP32 i2s_read example
* H2: Use PLL_48M_CLK in Timg driver and add imer_interrupt example
* Clean timer driver, add helper configure_src_clk and configure_wdt_src_clk methods
* H2: Add imer_interrupt example
* add helper methods for selecting default clk src
* Change PR number in the Changelog
* Add efuse field tables from IDF
* Add efuse fields constants generator
* Fix MAC field in efuse tables
* Add common efuse field impl
* Add efuse fields support for chips
* Add efuse changes to changelog
* Support for multicore async GPIO:
Use the correct registers depending on which core the interrupt is being
serviced on. Fixed a bug in the `esp32::gpio_intr` which would enable
the interrupt on both cores. It now enables the interrupt for the core
in which `listen()` is called.
* add changelog item
* Simplify GPIO interrupt status
* RISCV: Separate PLIC and non-PLIC
* De-duplicate code
* Write 0 to INTR_MAP again to disable peripheral interrupts
* Limit visibility of `get_assigned_cpu_interrupt`
* Create an `soc` module with a submodule for each chip, move `peripherals` in
* Move the `cpu_control` module into `soc`
* Move the `efuse` module into `soc`
* Refactor type definitions from `gpio` module into `soc`
* Put all embassy-related files in a common directory
* Change visibility of `GpioPin` constructor
