* update embassy in Cargo.toml and add embassy-time-driver
* fix embassy-time for esp-hal-common
* update CHANGELOG.md
* fix clippy warning by removing manual adc implimentation for esp32
* undo change, fixing clippy error by removing unused use statement
* remove embassy crates-io patches
* remove a remaining embassy patch
* Update embassy-time version in esp-hal-common/Cargo.toml
Co-authored-by: Scott Mabin <scott@mabez.dev>
* remove the remaining embassy patches
* remove embassy-time as a dependency for esp*-hal
---------
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Add `rt-riscv` and `rt-xtensa` features to `esp-hal-common` to allow enabling/disable runtime support
* Update the CI workflow to check the chip-specific HAL packages without default features
* Update `CHANGELOG.md`
* Update to `embedded-hal@1.0.0-rc.2` and friends, bump some other deps
* Update method name in `SetDutyCycle` trait implementation
* Implement `DelayNs` trait
* Update `CHANGELOG.md`
* Update `usb-device` as well
* Use latest `embassy-executor` release
* RISC-V executors
* Add multiprio example to RISC-V SoCs
* Check new examples
* Hack in support for generic queue
* Reserve SoftwareInterrupt0 for multicore thread-mode executors
* Merge interrupt executors
* Merge thread-mode executors
* Document the new features and expand on time drivers
* Main tasks don't have to return !
* Unify multiprio examples
* Undo C6 log output change
* Async read implementation for usb serial jtag
* Check the example in ci
* Add the example's required features
* Add changelog entry
* Improve the example
* Add examples for other boards
* Fix changelog
* Add required features for examples
* Force frame pointers for RISC-V chips
* Various dependency updates
* Update to latest published PACs and resolve build errors
* Top-level `README` updates
* Further clarify when `RUSCT_BOOTSTRAP=1` is required
* Fix Async UART
The uart handler was `writing` to the enable register instead of
`modify`, which meant any wake would see the cleared enabled bit and
think the event had occurred. This wasn't seen before the split of uart
because it was only possible to listen to one thing at a time.
This PR also removes the ReadBufferFull error in favour of returning the
max bytes in the buffer.
The serial examples has been updated to actually have some cross task
communication.
* changelog
* fix dev deps
* Make sure examples can build with defmt
* Remove duplicate example checks
* Fix examples
* Add changelog entry
* Actually build some examples with defmt feature enabled
* Add the defmt linker script in each package's build script
* Bump MSRV to 1.67, check with `defmt` feature enabled in MSRV checks where applicable
* Add `esp32c6-lp-hal-procmacros` package to VS Code workspace
* Update `CHANGELOG.md`
* Executor related touchups
* Make log optional
* Add defmt feature and derive on Debug structs
* Test both log drivers
* Update esp-println
* Document defmt msrv
* Update a bunch of dependencies
* Implement `embedded-io` and `embedded-io-async` traits for USB Serial JTAG
* Implement `embedded-io` and `embedded-io-async` traits for UART
* Fix `embassy_serial` examples
* Update CHANGELOG
* Address review comments
* direct vectoring support added
* provide minimal handlers for hooking the vector table directly
* changed direct vectoring interrupt enable interface to map to CPU interrupt
* direct vectoring interrupt nesting
* removed unused dependency
* added tentative c2 and c6 support for direct vector table hooking
* added direct vectoring examples
* added direct vectoring examples
* updated changelog
* added direct vectoring to CI
* Added H2 support and example, moved helpers to esp-hal-common
* Added H2 direct vectoring example to CI
* Removed remnants of removed feature
* C6 and H2 examples fixed
* C6 and H2 examples fixed
* C6 and H2 examples fixed
* Comment fixed
* Added preemption flag to RT
---------
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Small refactor to extract functions for setting up reads/writes
* Implement async capabilities for `I2C` driver
* Add async I2C examples for each supported chip
* Update CHANGELOG
* Initial async_{write|flush} implementations
- ESP32C3 + UART0 example
* Support UART1 & UART2
* Add examples for all chips
* reduce number of wakers depending on uart count
* Software interrupt support added, not sure if the code is good
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* prio based preemption only, vector table reverted
* prio based preemption only, vector table reverted
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed rare bug causing misaligned memory access when emulating atomics
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* broke something
* broke something
* fixed alignment bug
* Tentative: added support for interrupt preemption without involving the rt
* Added feature enabling priority based interrupt preemption
* Fixed failed merge
* Tagged preemption helpers with inline always
* Disable interrupts before restoring context to avoid ruining it
* Fix max priority edge case
* Fix broken merge
* Added examples for the remaining RISC-V ESPs
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp32c2-hal/examples/interrupt_preemption.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Example comments courtesy of @sethp
* Reverted irrelevant changes, raised high prio interrupt to max prio
* Rolling back an irrelevant change
* Rolling back an irrelevant change
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Moved imports to avoid warnings, moved functions to ram, moved interrupt disable to before prio threshold is restored
* Added preemption for the ESP32C6
* Moved helper functions into the relevant modules, changed threshold for ESP32C6 to machine mode one
* ESP32C6 Threshold register changed to machine mode one, corrected threshold set.
---------
Co-authored-by: sethp <seth.pellegrino@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
