* ground work for async dma (gdma only atm)
* Add async DMA (GDMA) - esp32c3/esp32c2
* Add Async SPI impl for esp32c3/c2
* Remove private modules from DMA
* add async spi example for esp32c3
* Switch to assoc wakers instead of a static array
* add support for esp32/esp32s2
* add support for esp32s3
* run fmt
* add c2 example, fix CI
* Remove redundant comments
* Add `is_listening` to `Pin` trait
* Add `Wait` impl for Gpio Input
* Add GPIO wait example for C3
* Ensure correct bank is accessed in interrupt
* Add esp32c2 wait example
* Add esp32s3 wait example
* Add esp32s2 wait example
* Add esp32 wait example
* Run fmt
* Add example to cargo tomls
* Add top level docs for embassy examples
* Mention the higher MSRV for async in the README
---------
Co-authored-by: Jesse Braham <jesse@beta7.io>
* start of pulse counter implementation
* implement interrupts
implement pcnt for esp32, esp32s2, and esp32s3
* implement pcnt for esp32s2
* fix esp32 PCNT signal names
* update PCNT register/fields for cleaned up PAC
* implement events/get_events (choosing what events interrupt)
* added pcnt example: simple encoder configuration
* restrict pcnt::channel::Channel::new() to super
* PcntPin -> PcntSignal
added range checks for thresholds and limits
* PcntSource is a better name I think
* handle error for PCNT Unit configure() in example
* update pac versions for status register change
* cargo fmt
* cargo fmt (examples)
* PcntSource now only stores the source id.
add a critical section to protect the ctrl & isr_en registers
* cargo fmt
* Add the peripheral module plus some helper macros in preparation
* peripheral macro
* Add peripheral generation macro
* Fixes after rebase
* Update the signature of Peripherals::take
* syncronise hello world example
* fmt the entire repo
Co-authored-by: Jesse Braham <jesse@beta7.io>
- Rename timg feature to timg0 to better refect which TG is being used
- Use the time_driver::TimerType in the signature of init to fix#268
- Update examples
- Fix CI features
- Add timg0 cfg to build.rs
* Add untested basic SHA for esp-sX/cX chips
* Fix ptr type inconsistency for S2
* Add ESP32 impl & fix process_buffer latch issue
* Add debug example for SHA accelerator
* Clean up no-op buffer prints
* Test vector parity (on esp32s3)
* Checkpoint for converting to alignment helper
* Finish refactoring & additional parity tests on esp32s3
* Remove core_intrinsics requirement for now
* Fix case where (src.len() % 4) == 3
* Finish sha2 example with performance comparison (12-61x speedup)
* Refactor ESP32 to alignment helper & Clean up example
* Prevent out-of-bounds reads in ESP32 version
* Revert Cargo debug changes
* Remove cargo config.toml
* Clean up example
* Remove common/rust-toolchain & ignore in future
* Might as well use actual size_of const
* Remove SHA512/SHA384 for C2/C3
* Directly import nb::block! to remove unused import warning & fix c2 feature detect
* Remove stray newlines
* Fix esp32c2 having SHA256
* ESP32 also has SHA384
* Remove comments that don't have a purpose
* Clean up example & finish() handling
* Add examples & add ESP32 free()
* Update C2/C3 examples to show accurate algorithm used
* Fix busy check for ESP32
* Remove outdated TODO comment
* Update PAC for ESP3 and (actually) fix busy check
* Refactor ESP32 version to reduce search space
* Add debug printlns to sha example & clean up comments
* Fix ESP32 version, finally
Co-authored-by: ferris <ferris@devdroplets.com>
Co-authored-by: Jesse Braham <jesse@beta7.io>
* wip: timg embassy driver
- read_raw on timg renamed to now()
- timg initialized and stored in static for use in the embassy driver
- timg sets alarm value
- untested whether alarms actually trigger
* TIMG timer driver for esp32, esp32s3
- Adds the timg timer block as a time driver for embassy
- Not enabled on the C3 as it only has one timer block, better to use
systimer
- s2 example added but can't build due to atomic requirements in
futures-core
* Add S2 atomic support with emulation, fixup embassy support for the S2
* Move executor & static-cell to dev deps. Make eha optional
* Add c2 support, run fmt
* Update to crates.io embassy releases
* Update eha
* update timg time driver to new trait
* Remove exception feature of esp-backtrace and use the user handler for backtracing
* Add async testing workflow
* Update systick example
* Fix S2 examples
* Update xtensa-toolchain
* set rustflags for s2 target
* Disable systick for esp32s2 until we can fix the noted issues
* review improvements
- Fix intr prio array being off by one
- emabssy time prio interrupt set to max prio
- use cfg instead of feature for systick detection
* Update example time delays
* WIP: common/spi: Implement `SpiDevice`
to get shared access to an SPI bus directly via the HAL.
* WIP: common/spi: add SpiBusDevice::new
to create instances via a function call.
* esp32/examples: Add example for spi device trait
* common/spi: Finish "SpiDevice" implementation
for esp32. Abandons the approach of having the user pass in some generic
mutex in favor of creating the Mutex as part of the API so it isn't
exposed to the user in the first place.
* common/spi: Add more thorough docs
* esp32/examples: Fix example for eh1 "SpiDevice"
* common/spi: Implement `SpiDevice` for xtensa arch
and move the code into a submodule that is fenced with conditional
compilation directives.
* esp32/examples: Update spi device example
to the changed APIs for the timers and clocks, and add more transmission
tests to the example code.
* common/spi: Create devices from buscontroller
directly, instead of offering only the `new` method.
* common/spi: Finish `SpiBusDevice` trait
from embedded-hal 1.0.0-alpha.8.
* esp32: Update `SpiBusDevice` usage example.
* common/spi: Fix mutex types for xtensa32 esp
because the esp32/esp32s3 can use `SpinLockMutex`, whereas the esp32s2
has access only to `CriticalSectionMutex`.
* common/spi: Implement `SpiBusDevice` for riscv
based esp32c3.
* general: Add examples for spi device loopback
to all esp variants.
* common: Use esp_backtrace in spi_eh1_device examples
* common/spi: Update module documentation.
* common/spi: Use `critical_section::Mutex`
to unify locking across all esp variants.
* esp32c3-hal: Fix spi device example
* esp32c3/examples: Fix typo in used spi pins
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* CS impl
* use CS Mutex in C3 examples
* use CS Mutex in S2 examples
* Update esp32 example
* run fmt
* Update S3 examples
* Remove uses of unsafe where no longer required
* use esp_backtrace in examples
* fix import & fmt once more
* Bump MSRV to 1.60.0
Co-authored-by: Jesse Braham <jesse@beta7.io>
* common/spi: Turn fifo size into const
instead of hard-coding it into the code in various places.
* common/spi: Alias `write_bytes` to `send_bytes`
since they share the same interface and the same code anyway.
* common/spi: Implement `read_bytes`
as counterpart to `send_bytes` that is responsible only for reading
bytes received via SPI.
* common/spi: Rewrite `transfer`
to use `send_bytes` and `read_bytes` under the hood and remove duplicate
code.
* common/spi: Create submodule for embedded_hal_1
that is re-exported when the `eh1` feature flag is active. This removes
lots of duplicate `#[cfg(...)]` macros previously part of the code.
* common/spi: Implement `SpiBus` and `SpiBusWrite`
traits from the `embedded-hal 1.0.0-alpha.8`.
* common/spi: Make `mosi` pin optional
* esp32-hal: Add new SPI example with `eh1` traits
* esp32-hal/examples/spi_eh1: Add huge transfer
and bump the SPI speed to 1 MHz.
* common/spi: Apply rustfmt
* common/spi: Use `memcpy` to read from registers
This cuts down the time between consecutive transfers from about 2 ms
to less than 1 ms.
* WIP: common/spi: Use `ptr::copy` to fill write FIFO
cutting down the time between transfers from just below 1 ms to ~370 us.
The implementation is currently broken in that it will always fill the
entire FIFO from the input it is given, even if that isn't FIFO-sized...
* common/spi: Add more documentation
* esp32/examples/spi_eh1: Fix `transfer_in_place`
* esp32/examples/spi_eh1: Add conditional compile
and compile a dummy instead when the "eh1" feature isn't present.
* esp32-hal: Ignore spi_eh1 example
in normal builds, where the feature flag "eh1" isn't given. Building the
example directly via `cargo build --example spi_eh1_loopback` will now
print an error that this requires a feature flag to be active.
* common/spi: Use `write_bytes`
and drop `send_bytes` instead. Previoulsy, both served the same purpose,
but `send_bytes` was introduced more recently and is hence less likely
to cause breaking changes in existing code.
* common/spi: Fix mosi pin setup
* Add SPI examples with ehal 1.0.0-alpha8 traits
to all targets.
* common/spi: Fix `read` behavior
The previous `read` implementation would only read the contents of the
SPI receive FIFO and return that as data. However, the `SpiBusRead`
trait defines that while reading, bytes should be written out to the bus
(Because SPI is transactional, without writing nothing can be read).
Reimplements the `embedded-hal` traits to correctly implement this
behavior.
* common/spi: Use full FIFO size on all variants
All esp variants except for the esp32s2 have a 64 byte FIFO, whereas the
esp32s2 has a 72 byte FIFO.
* common/spi: Use common pad byte for empty writes
* common/spi: Fix reading bytes from FIFO
by reverting to the old method of reading 32 bytes at a time and
assembling the return buffer from that. It turns out that the previous
`core::slice::from_raw_parts()` doesn't work for the esp32s2 and esp32s3
variants, returning bogus data even though the correct data is present
in the registers.
* common/spi: Fix typos
* examples: Fix spi_eh1_loopback examples
* esp32: Fix typo in Frequency word in some identifiers
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add support for PLL clock configuration
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* clock: Move definition of Clock types to common level
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add support for RTC Clock configuration
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add example for the RTC Watchdog Timer driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* RISCV interrupt vectoring
- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes
* remove .vscode files
* Support vectored edge interrupts
This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.
* fix all examples to use vectoring
* doc & cleanup
* run handlers from ram
* make xtensa::interrupt::vectored private, we rexport public items
* fix default handlers
* pass interrupt into EspDefaultHandler
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
