Previously it assumed that the entry point was allocated at the
beginning of the ".rwtext" output section, which is not always true.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
If bss contained anything a linker error was emitted about overlapping
sections. Moving the .bss section to after the .rwtext, and adding a dummy
section to pad data bus access to the bss section fixes this.
* RISCV interrupt vectoring
- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes
* remove .vscode files
* Support vectored edge interrupts
This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.
* fix all examples to use vectoring
* doc & cleanup
* run handlers from ram
* make xtensa::interrupt::vectored private, we rexport public items
* fix default handlers
* pass interrupt into EspDefaultHandler
