For now, only the -c3.
---
Open up LEDC fade support to all chips.
The C6 chip needs some special handling because its fade registers also
handle gamma, and the ESP chip needs some special handling because it
has two banks of channels. The code to handle these is already present
in channel.rs, but needs to be copied and adapted. Do that, and drop
all the esp32c3 feature checks.
---
Add a function to poll the duty-fade state
Use the unmasked interrupt bit in the LEDC register block, since that
will get updated by the hardware whether or not we've connected anything
to the interrupt source. Also be sure to clear that bit before starting
a new fade, so it's always clear while fading.
This will allow dumb (non-async-code) polling of the fade state after
one is started by the start_duty_fade API.
---
Fix non-C3 devices to use the right int_raw bits
These are inconsistently named between the esp32 variants.
---
Add examples of hardware duty-cycle fading
Just a relatively simple zero to 100 and back to zero, over a total of 2
seconds, to get a breathing effect.
This does make the main loop{} have a 2-second period instead of the
current nearly-zero period, but nothing else is happening so that's
fine.
---
Fix two bugs in hardware fading
When figuring out how many duty-cycle changes need to happen per counter
overflow, we need to use the absolute value of the difference between
the start and end duty values, not the raw difference. When fading from
(e.g.) 100% to 0, this will overflow, and both the debug-mode panic and
the release-mode wrapping behavior give the wrong delta value.
So calculate an absolute value difference first, and use that.
Then, when running through the while loop that allocates bits between
pwm_cycles and duty_cycle, the check on pwm_cycles was wrong -- since
the value reduces each time through the loop, we need to keep looping as
long as it's *above* some threshold, not below.
---
Simplify and refactor duty-cycle fade code
I'm not sure if this will fix the extremely-short fade times that we're
seeing with the older code, but we'll see.
Move all the calculations out of the ChannelHW implementations, and make
those *just* set registers. The calculations are the same for all chip
variants, so don't need to be duplicated for each chip feature, like the
register macros are.
Change the calculations from a loop doing bit shifts, to an explicit
division and a couple of range checks. This way we can get a lot closer
to the requested percentages and durations.
Use the u32::abs_diff function instead of open-coding it (now that I see
it exists).
Use u16::try_from() to limit the range of values, and use try_into<u16>
and map_err and the ? operator to more clearly handle numbers out of
range.
Drop the Result<> return type from the ChannelHW function, as it can't
fail anymore.
Fix the duty_range value -- before, when duty_exp was (say) 8,
duty_range would be 256, and if one of the *_duty_pct values was 100,
the start or end duty value would be too big. The range of start and
end duty values is 0..255, so we have to subtract one to handle 100%.
Finally, add a comment on the is_duty_fade_running{,_hw} methods.
---
Some fades can't work; return errors for them.
Add a new Error enum value with a sub-error enum with more details.
Return it from the error cases in the fade method.
If the calculated cycles_per_step is more than 10 bits, fail as well;
the field in the register is only 10 bits wide.
Fix all the examples to run a 1-second fade instead of a 2-second, since
the 2-second fade will run into this error. (Assert that, as well.)
---
When fading on a -c6 chip, set two more registers
The gamma functionality of -c6 chips needs two more fields set. One
tells the chip how many gamma stages it should iterate through, but we
only implement linear fading, so always use 1. The other tells the chip
to latch the value of the other gamma registers into the chosen slot, so
even though its value never changes, the write needs to happen.
---
Add changelog entry
* Create an `soc` module with a submodule for each chip, move `peripherals` in
* Move the `cpu_control` module into `soc`
* Move the `efuse` module into `soc`
* Refactor type definitions from `gpio` module into `soc`
* Put all embassy-related files in a common directory
* Change visibility of `GpioPin` constructor
* Create the `esp32c6-hal` package
* Teach `esp-hal-common` about the ESP32-C6
* Get a number of peripheral drivers building for the ESP32-C6
bckup
initial clocks_ii
* Create the `esp32c6-hal` package
C6: update
* Simplify and fix the linker script
update
* C6: add I2S
* Create the `esp32c6-hal` package
* Teach `esp-hal-common` about the ESP32-C6
* Get a number of peripheral drivers building for the ESP32-C6
bckup
initial clocks_ii
* Create the `esp32c6-hal` package
* C6: update
* Simplify and fix the linker script
* update
* C6: add I2S
* update
* C6 Interrupts
* C6: Update build.rs, linker scripts and initial examples
* C6: RMT
* Fix interrupt handling
* Fix `ClockControl::configure`
* C6: revert to I2S0 instead of just I2S
* C6: rebase and update
* RTC not buildable
* Implement RWDT and SWD disable
* C6: working LEDC
* C6: working RMT
* C6: add aes
* C6: add mcpwm
* C6: add rtc_cntln - not finished
* C6: update and formatting
* C6: add pcnt
* C6: add examples and format
* Remove inline assembly, fix interrupts and linker scripts
* Remove unused features, update cargo config for atomic emu, misc cleanup
* Get ADC building and example "working" (as much as it ever does)
* Remove a bunch of unused constants which were copied from ESP-IDF
* The `mcpwm` example now works correctly
* Get `TWAI` peripheral driver building for C6
* Clean up the `rtc_cntl` module and get all the other HALs building again
* Add the C6 to our CI workflow
* Fix various things that have been missed when rebasing
Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`)
* C6: Small updates in wdt (#1)
* C6: Update WDT
* C6: Update examples with WDT update
* Update `esp-println` dependency to fix build errors
* Fix formatting issues causing pre-commit hook to fail
* Get some more examples working
* Working `ram` example
* Sync with changes in `main` after rebasing
* Working `embassy_spi` example
* Use a git dependency for the PAC until we publish a release
* Fix I2S for ESP32-C6
* Fix esp32c6 direct boot (#4)
* Add direct boot support for C6
* Fix direct boot for c6
- Actually copy into rtc ram
- remove dummy section that is no longer needed (was just a waste of
flash space)
- Move RTC stuff before the no load sections
* Update RWDT and refactor RTC (#3)
* C6: Update RWDT and add example, refactor RTC and add not-really-good example
* Update based on review comments, resolve bunch of warnings and run cargo fmt
* Update C6 esp-pacs rev commit
* Fix clocks_ll/esp32c6.rs
* Fix riscv interrupts
* Remove clock_monitor example for now
* RAM example works in direct-boot mode
* Add a TODO for &mut TIMG0 and cargo fmt
* Fix linker script after a bad rebase
* Update CI and Cargo.toml embassy required features
* use riscv32imac-unknown-none-elf target for C6 in CI
* change default target to riscv32imac-unknown-none-elf
* add riscv32imac-unknown-none-elf target to MSRV job
* another cleanup
---------
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Jesse Braham <jesse@beta7.io>
* Make required changes to include new `RADIO` peripheral
* Use published versions of PAC and `esp-println`
* Use the correct target extensions (`imac`)
* Fix the super watchdog timer, plus a few more examples
* Fix UART clock configuration
* Make sure to sync UART registers when configuring AT cmd detection
* Disable APM in direct-boot mode
* Address a number of review comments
* Fix `SPI` clocks and `rtc_watchdog` example (#6)
* fix SPI clocks
* run cargo fmt
* Add comment about used default clk src
* Fix rtc_watchdog example in BL mode
* run cargo fmt
* Update rtc_watchdog example that it works in DB mode
* README and example fixes/cleanup
* Add I2C peripheral enable and reset
* Fix `ApbSarAdc` configuration in `system.rs`
---------
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Peripheral ref/sha (#312)
* Add SHA to list of peripherals to be created
* Refactor SHA peripheral to use PeripheralRef
* Update SHA examples to get them building again
* Fix async time drivers
* Fix usb otg
* Fix s3
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Add RNG to list of peripherals to be created
* Refactor RNG driver to use PeripheralRef
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Update the build script to inject a configuration value for the enabled chip
* Update all cfg gates to use the new symbols instead of the chip features
* Inject architecture and core count symbols as well, update as needed
* Organize the imports and exports of `esp-hal-common`
* CS impl
* use CS Mutex in C3 examples
* use CS Mutex in S2 examples
* Update esp32 example
* run fmt
* Update S3 examples
* Remove uses of unsafe where no longer required
* use esp_backtrace in examples
* fix import & fmt once more
* Bump MSRV to 1.60.0
Co-authored-by: Jesse Braham <jesse@beta7.io>
* esp32: Fix typo in Frequency word in some identifiers
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add support for PLL clock configuration
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* clock: Move definition of Clock types to common level
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add support for RTC Clock configuration
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
* esp32c3: Add example for the RTC Watchdog Timer driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
