* Unify the system peripheral
Whilst the PCR, SYSTEM and DPORT peripherals are different, we currently
use them all in the same way. This PR unifies the peripheral name in the
hal to `SYSTEM`. The idea is that they all do the same sort of thing, so
we can collect them under the same name, and later down the line we can
being to expose differences under an extended API.
The benifits to this are imo quite big, the examples now are all identical,
which makes things easier for esp-wifi, and paves a path towards the
multichip hal.
Why not do this in the PAC? Imo the pac should be as close to the
hardware as possible, and the HAL is where we should abstractions such
as this.
* changelog
* Make the example work
* Make GPIO wakeups work
* Add example
* revert hello_rgb change
* Clean up the first hacky version
* Fix example warnings
* Add changelog entry
* Fix example comment
* Stop skipping rustfmt
* Unify the xtal frequency features for ESP32 and ESP32-C2
* Group and re-organize features for `esp-hal-common`
* Update `esp-hal-smartled` and fix its CI check
* Update `CHANGELOG.md`
* Update feature names in documentation
* Adding async support for RSA peripheral
* Add esp32 support (doesn't work properly yet)
* Xtensa chips are supported (except of esp32)
Add modular multiplication for esp32
Adding a CHANGELOG entry
Rebase issue fix
* Code cleanup
* Add `.await` on `RsaFuture::new()` calls
* Refactor and rebase
Made `read_results` functions to be `async`, got rid of `nb` usage
* Change API methods naming + refactor `start_step2` method
* Adjust example to the API change + documentation
* Code cleaning + refactoring
Update examples
* No longer publicly expose the `PeripheralClockControl` struct
* Update examples as needed to get things building again
* Update CHANGELOG.md
* Address review feedback, fix a warning
* Use a critical section for all devices other than the ESP32-C6/H2, as they modify multiple registers
* Rebase and update `etm` driver to fix build errors
* Make ADC reads return u16s, not generic types
* Changelog entry
* Add the PR number to the changelog
---------
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Ensure that uart is configured to account for clock changes, not just boot defaults
* fix examples
* changelog
---------
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Add support for splitting esp32 uart into TX and RX
* Keeps existing API for uart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to embassy-rs nRF/stm32/rp for getting indepdendent TX and RX
parts
* Implements e-h traits for TX and RX types
* Add esp32s3 example
* finish implementing
* rebase examples
* declare new examples
* fix fmt
* rebase on 0.12.0
* fix fmt
* fix fmt
* merge embassy_serial_split example with embassy_serial
* fix changelog
* fix changelog
* Add ECC driver for ESP32C2 and ESP32C6
* Add ECC example for ESP32C2 and ESP32C6
* Add and modify dependencies
* ESP32H2: Add ECC driver support
* ESP32H2: Add ECC example
* ESP32C2 and ESP32C6: clean examples
* changelog
* refactor: remove enable_interrupt() and clear_interrupt()
* refactor: remove ugly if/else logic for padding
* Bump MSRV to 1.67, check with `defmt` feature enabled in MSRV checks where applicable
* Add `esp32c6-lp-hal-procmacros` package to VS Code workspace
* Update `CHANGELOG.md`
* Macro to load LP core code
* Fix imports, add CHANGELOG.md entry
* Avoid code warning
* Omit path from function signature
* More error checking
* Clippy fix
* Include the ELF used by the lp_core_basic example
* Make object dependency optional
* Use 1.65 for RISCV MSRV check
* Use RUSTC_BOOTSTRAP for RISCV MSRV check
* Remove the pre-compiled LP core example
* Pin toml_edit in esp32c6-lp-hal-procmacro
* Executor related touchups
* Make log optional
* Add defmt feature and derive on Debug structs
* Test both log drivers
* Update esp-println
* Document defmt msrv
* Executor related touchups
* Fix typos
* Clean up DAC, remove hidden public API
* Clean up ADC
* Clean up analog peripheral reexports
* Properly hide rmt macros
* Rework watchdog timer drivers to allow enabling/disabling and feeding without traits
* Disable all watchdogs prior to `main` using the `__post_init` hook
* Update all watchdog-related examples
* Update CHANGELOG
* Address review comment
* Hide internal-only RMT macros from documentation
* Document the features of each chip-specific HAL package
* Document the supported image formats for relevant packages
* Update a bunch of dependencies
* Implement `embedded-io` and `embedded-io-async` traits for USB Serial JTAG
* Implement `embedded-io` and `embedded-io-async` traits for UART
* Fix `embassy_serial` examples
* Update CHANGELOG
* Address review comments
* Use all remaining memory for stack(s)
* Remove HEAP related code from RISCV linker scripts
* Fix direct-boot / mcu-boot linker scripts
* Use a statically allocated stack for core-1
* direct vectoring support added
* provide minimal handlers for hooking the vector table directly
* changed direct vectoring interrupt enable interface to map to CPU interrupt
* direct vectoring interrupt nesting
* removed unused dependency
* added tentative c2 and c6 support for direct vector table hooking
* added direct vectoring examples
* added direct vectoring examples
* updated changelog
* added direct vectoring to CI
* Added H2 support and example, moved helpers to esp-hal-common
* Added H2 direct vectoring example to CI
* Removed remnants of removed feature
* C6 and H2 examples fixed
* C6 and H2 examples fixed
* C6 and H2 examples fixed
* Comment fixed
* Added preemption flag to RT
---------
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update to latest (unreleased) versions of PACs
* Update `SDMCC` peripheral to `SDHOST` for ESP32
* Fix `USB_DEVICE` interrupts
* Fix references to various renamed GPIO fields for ESP32-S2
* Update and re-organize the `rmt` driver
* Update CHANGELOG
* Remove the old `pulse_control` driver
* Update `esp-hal-smartled` to use the new `rmt` driver instead
* Update the `hello_rgb` example for each chip
* Update CHANGELOG
* Add Initial MCPWM DeadTime configuration
* Add option to use other channel for action trigger
* Fix build for non-esp32s3 (register name difference)
* Fix changelog build & add a way to update RED/FED after construction
* Fix regs
* Implementing ASYNC features for USB_SERIAL_JTAG (work in progress)
Fix: Interrupt name
* Async works for USB Serial/JTAG
PS. : Yet only for esp32c3, we need to update PACs
Temporary example fix
* Adjustment for different chips
+ Update examples according to upstream
+ Code cleaning
Rust format
* Add record to the CHANGELOG
* Code cleaning, getting rid of useless generic argument
Typo fix
Fix fmt
* deep sleep api for esp32
* move to list of wakeup sources
* improve Ext0WakeupSource - still WIP
* add deep sleep with timer wakeup example
add Ext0 wakeup source (WIP/Non-working)
* removed alloc (using heapless now)
* Sleep: ext0 wakeup working
* add sleep_timer_ext0 example
* API change: move sleep into RTC as sleep, sleep_deep, sleep_light
* fix sleep examples for new API
* sleep only implemented for esp32 at this time
* sleep only implemented for esp32 at this time
* Implement a simple RTCPin trait to support sleep
* implement RTCPin for all xtensa SOC
* cargo fmt & update changelog
* fix change log order (accidentally swaped during rebase)
* implement Drop for Ext0WakeupSource
* added Ext1 wakeup source
* cargo fmt
* healpess was unused, removed
* fix pase macro usage
* adc_cal: c2: Add efuse functions for reading calibration
* adc_cal: c3: Add efuse functions for reading calibration
* adc_cal: c6: Add efuse functions for reading calibration
* adc_cal: Add extra traits to support calibration
- `AdcCalScheme<ADCI>` implemented for each calibration scheme (basic, linear, curved)
- `AdcCalEfuse` implemented for each ADC unit to get calibration data from efuse bits
* adc_cal: Add basic ADC calibration scheme
Basic calibration is related to setting some initial bias value to ADC unit.
Such values usually is stored in efuse bit fields but also can be measured
in runtime by connecting ADC input to ground internally.
* adc_cal: Add line fitting ADC calibration scheme
This scheme also includes basic calibration and implements gain correction based
on reference point.
Reference point is a pair of reference voltage and corresponding mean raw ADC
value. Such raw values usually is stored in efuse bit fields for each supported
attenuation.
Possibly it also can be measured in runtime by connecting ADC to reference
voltage internally.
* adc_cal: Add curve fitting ADC calibration scheme
This scheme also includes basic and linear and implements final polynomial error
correction.
* adc_cal: riscv: Add ADC calibration implementation for riscv chips
* adc_cal: c2: Add calibrated ADC reading example
This example uses line fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: c3: Add calibrated ADC reading example
This example uses curve fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: c6: Add calibrated ADC reading example
This example uses curve fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: riscv: Add changelog entry for ADC calibration
* Introduce a trait for DMA channels
This trait is then used to hold types related to the particular DMA channel. This change allows us to simplify user-facing types.
* Remove private type from I2s
* Remove redundant spi3 example, update examples
* Merge markdown sections
* Add changelog entry
* Add ROM MD5 definitions in linker and devices
* Add initial MD5 support
* Implement traits and add comments to MD5 module
* Add MD5 example to ESP32-C3
* Test MD5 context on the quick brown fox
* Implemenr From<Context> for Digest
* Add MD5 to the rest of the examples
* Add docs for MD5
* Remove #[repr(transparent)] from md5::Digest
* Update CHANGELOG.md
* Create issue_handler.yml
* No longer re-export `embedded-hal`, hide exported macros in documentation
* Add simple package-level documentation for each HAL package
* Clean up/simplify re-exports
* Fix the examples that I broke
* Ensure top-level modules/types/functions have doc comments
* Update CHANGELOG
* Re-export the `soc::psram` module where available
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
This is temporary measure, as the problem cannot be solved cleanly right
now.
The issue is that the msrv check uses the stable compiler, which uses a
stable cargo. With a stable cargo, the unstable `build-std` option is
not respected within `.cargo/config.toml`. This means `core` is never
rebuilt with the atomic cfg flags so we get this error when building log
version 0.4.19. The 0.4.19 release uses the atomic cfg flags instead of
a custom build script, so by switching back to 0.4.188888888 we can avoid this
issue... for now at least.
* H2: Add initial i2s support and i2s_read and i2s_sound examples
* Add I2S_SCLK and I2S_DEFAULT_CLK_SRC constants for all chips
* Update I2S driver
* fmt
* Add changelog
* Change DIN GPIO17 to GPIO14 in ESP32 i2s_read example
* First README prototype
* README update
Fixed link, uncommented Matrix link, made some preparations before docs will be posted
* Added a change to CHANGELOG
* typo: return header sign back
* Process Fosc frequencies for ECO1+ ESP32C6 chips
e3148369f3
* Final update for FOSC calibration (ESP32C6)
+ fixed few errors
* Fix format + add update to Changelog
Formatting
Formatting (1)
* H2: Use PLL_48M_CLK in Timg driver and add imer_interrupt example
* Clean timer driver, add helper configure_src_clk and configure_wdt_src_clk methods
* H2: Add imer_interrupt example
* add helper methods for selecting default clk src
* Change PR number in the Changelog
* Add efuse field tables from IDF
* Add efuse fields constants generator
* Fix MAC field in efuse tables
* Add common efuse field impl
* Add efuse fields support for chips
* Add efuse changes to changelog
* Async GPIO multibank fix
- Removes dead code from the default impl of the BankAccess trait
- Adds one new function to the async module to control the interrupt
enable for any pin
* Add changelog entry
* Simplify the `Delay` driver, derive `Clone` and `Copy`
The RISC-V and Xtensa implementations of the delay functionality are both safe to access from multiple contexts, and the `Delay` struct does not take ownership of any peripheral struct, so `Delay` is safe to clone/copy
* Update the CHANGELOG
* Update the `GDMA` driver to support the ESP32-H2
* Update the `SPI` driver to support the ESP32-H2
* Add `SPI` examples for ESP32-H2
* Update CHANGELOG
* Remove copy-pasted references to ESP32-C6
* Update GPIO pins used in SPI examples, add `qspi_flash` example
* Update SPI clock configuration to produce correct clock rate
* Correct comment regarding clock source frequency
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
* H2: Add PLL_48M_CLK src to ClockControl and RawClocks
* H2: Use PLL_48M_CLK as SPI clk src
* H2: cleanup commented block in SPI driver
* H2: update docs comment in embassy_spi example
* fmt
* Add a new line in embassy_spi example
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
