* Initial async_{write|flush} implementations
- ESP32C3 + UART0 example
* Support UART1 & UART2
* Add examples for all chips
* reduce number of wakers depending on uart count
* Software interrupt support added, not sure if the code is good
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* prio based preemption only, vector table reverted
* prio based preemption only, vector table reverted
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed rare bug causing misaligned memory access when emulating atomics
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* broke something
* broke something
* fixed alignment bug
* Tentative: added support for interrupt preemption without involving the rt
* Added feature enabling priority based interrupt preemption
* Fixed failed merge
* Tagged preemption helpers with inline always
* Disable interrupts before restoring context to avoid ruining it
* Fix max priority edge case
* Fix broken merge
* Added examples for the remaining RISC-V ESPs
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp32c2-hal/examples/interrupt_preemption.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Example comments courtesy of @sethp
* Reverted irrelevant changes, raised high prio interrupt to max prio
* Rolling back an irrelevant change
* Rolling back an irrelevant change
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Moved imports to avoid warnings, moved functions to ram, moved interrupt disable to before prio threshold is restored
* Added preemption for the ESP32C6
* Moved helper functions into the relevant modules, changed threshold for ESP32C6 to machine mode one
* ESP32C6 Threshold register changed to machine mode one, corrected threshold set.
---------
Co-authored-by: sethp <seth.pellegrino@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update `embedded-hal-1` and `embedded-hal-nb` dependencies to latest versions
* Update the `Delay` and `I2c` trait implementations
* Update the `SpiDevice` trait, implement `SpiDeviceRead` and `SpiDeviceWrite`
* Add README, improve documentation for `esp-hal-procmacros`
* Improve documentation for `esp-hal-smartled`
* Use esp-rs logo for all packages' documentation
* esp32 & esp32s2 sharing scripts
* add wokwi files
* Add fixup section for esp32s2, fix ordering of sectino includes
* Remove debug asm file
* Use shared linker scripts for s3 with fixups
* Add external.x sections back
* Move ld scripts into esp-hal-common
* esp32c3 unified linker scripts
- rework original c3 script to use the xtensa named sections
(e.g, _SECTIONNAME_start)
- Add fixups in esp32c3 specific linker
- Remove useless text section start and end (not required when using any
form of bootloader)
* Add RTC alias'. Move some shared fixups to a file
* comment and cleanup
* unify c2 linker script
* unify c6 linker script
* remove debug configs
* use new esp-riscv-rt
* fmt
* align db symbol names
* fix s3 db
* Add additional `cfg` gates to re-exports in `esp-hal-common`
This leaves only `clock`, `delay`, `peripheral`, `prelude`, `rom`, and `soc` *not* behind `cfg`s
* Simplify the prelude, update its `cfg`s, and re-export some missing traits
* Update various dependencies
* Extract the `esp-hal-smartled` package
This (finally) eliminates the `esp_hal_common::utils` module!
* Remove all references to the old `smartled` feature from CI
* RISCV: Separate PLIC and non-PLIC
* De-duplicate code
* Write 0 to INTR_MAP again to disable peripheral interrupts
* Limit visibility of `get_assigned_cpu_interrupt`
* Move some linker scripts into `esp-hal-common` and update the build script
* Move `EspDefaultHandler` and `DefaultHandler` definitions into `esp-hal-common`
* Re-export everything from `esp-hal-common`
* Add a couple cfg symbols, cleanup/organize some exports/modules
