From fe03af805bf9c4ca065322039c74c6045953843f Mon Sep 17 00:00:00 2001
From: Robert Wiewel <dev@ducktec.de>
Date: Fri, 25 Feb 2022 23:27:35 +0100
Subject: [PATCH] Fix mutability assumptions of RTC_CNTL for ESP32C3

---
 esp32c3-hal/examples/blinky.rs         | 2 +-
 esp32c3-hal/examples/gpio_interrupt.rs | 2 +-
 esp32c3-hal/examples/hello_world.rs    | 2 +-
 esp32c3-hal/src/rtc_cntl.rs            | 8 ++++----
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/esp32c3-hal/examples/blinky.rs b/esp32c3-hal/examples/blinky.rs
index 200275968..dadd1f0fd 100644
--- a/esp32c3-hal/examples/blinky.rs
+++ b/esp32c3-hal/examples/blinky.rs
@@ -11,7 +11,7 @@ fn main() -> ! {
 
     // Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
     // the RTC WDT, and the TIMG WDTs.
-    let rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
+    let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
     let mut timer0 = Timer::new(peripherals.TIMG0);
     let mut timer1 = Timer::new(peripherals.TIMG1);
 
diff --git a/esp32c3-hal/examples/gpio_interrupt.rs b/esp32c3-hal/examples/gpio_interrupt.rs
index 00bf48413..8a7938007 100644
--- a/esp32c3-hal/examples/gpio_interrupt.rs
+++ b/esp32c3-hal/examples/gpio_interrupt.rs
@@ -33,7 +33,7 @@ fn main() -> ! {
 
     // Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
     // the RTC WDT, and the TIMG WDTs.
-    let rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
+    let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
     let mut timer0 = Timer::new(peripherals.TIMG0);
     let mut timer1 = Timer::new(peripherals.TIMG1);
     let serial0 = Serial::new(peripherals.UART0).unwrap();
diff --git a/esp32c3-hal/examples/hello_world.rs b/esp32c3-hal/examples/hello_world.rs
index e38ebaaf3..bd744d060 100644
--- a/esp32c3-hal/examples/hello_world.rs
+++ b/esp32c3-hal/examples/hello_world.rs
@@ -12,7 +12,7 @@ use riscv_rt::entry;
 fn main() -> ! {
     let peripherals = Peripherals::take().unwrap();
 
-    let rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
+    let mut rtc_cntl = RtcCntl::new(peripherals.RTC_CNTL);
     let mut serial0 = Serial::new(peripherals.UART0).unwrap();
     let mut timer0 = Timer::new(peripherals.TIMG0);
     let mut timer1 = Timer::new(peripherals.TIMG1);
diff --git a/esp32c3-hal/src/rtc_cntl.rs b/esp32c3-hal/src/rtc_cntl.rs
index a2e28733f..70d7dfed1 100644
--- a/esp32c3-hal/src/rtc_cntl.rs
+++ b/esp32c3-hal/src/rtc_cntl.rs
@@ -9,7 +9,7 @@ impl RtcCntl {
         Self { rtc_cntl }
     }
 
-    pub fn set_super_wdt_enable(&self, enable: bool) {
+    pub fn set_super_wdt_enable(&mut self, enable: bool) {
         self.set_swd_write_protection(false);
 
         self.rtc_cntl
@@ -19,7 +19,7 @@ impl RtcCntl {
         self.set_swd_write_protection(true);
     }
 
-    fn set_swd_write_protection(&self, enable: bool) {
+    fn set_swd_write_protection(&mut self, enable: bool) {
         let wkey = if enable { 0u32 } else { 0x8F1D_312A };
 
         self.rtc_cntl
@@ -27,7 +27,7 @@ impl RtcCntl {
             .write(|w| unsafe { w.swd_wkey().bits(wkey) });
     }
 
-    pub fn set_wdt_enable(&self, enable: bool) {
+    pub fn set_wdt_enable(&mut self, enable: bool) {
         self.set_wdt_write_protection(false);
 
         if !enable {
@@ -41,7 +41,7 @@ impl RtcCntl {
         self.set_wdt_write_protection(true);
     }
 
-    fn set_wdt_write_protection(&self, enable: bool) {
+    fn set_wdt_write_protection(&mut self, enable: bool) {
         let wkey = if enable { 0u32 } else { 0x50D8_3AA1 };
 
         self.rtc_cntl