Add RMT hil-test (#1665)

* Add RMT hil-test

* Fix compilation error on ESP32/ESP32-S2

esp-hal/src/rmt.rs

@@ -115,7 +115,7 @@ pub enum Error {
 /// Convenience representation of a pulse code entry.
 ///
 /// Allows for the assignment of two levels and their lengths
-#[derive(Clone, Copy, Debug, Default)]
+#[derive(Clone, Copy, Debug, Default, PartialEq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct PulseCode {
     /// Logical output level in the first pulse code interval

hil-test/Cargo.toml

@@ -52,6 +52,10 @@ harness = false
 name    = "spi_full_duplex_dma"
 harness = false
 
+[[test]]
+name    = "rmt"
+harness = false
+
 [[test]]
 name    = "rsa"
 harness = false

hil-test/tests/rmt.rs

@@ -0,0 +1,114 @@
+//! RMT Loopback Test
+//!
+//! It's assumed GPIO2 is connected to GPIO4
+
+//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
+
+#![no_std]
+#![no_main]
+
+use defmt_rtt as _;
+use esp_backtrace as _;
+use esp_hal::{
+    clock::ClockControl,
+    gpio::Io,
+    peripherals::Peripherals,
+    prelude::*,
+    rmt::{PulseCode, Rmt, RxChannel, RxChannelConfig, TxChannel, TxChannelConfig},
+    system::SystemControl,
+};
+
+#[cfg(test)]
+#[embedded_test::tests]
+mod tests {
+    use super::*;
+
+    #[init]
+    fn init() {}
+
+    #[test]
+    #[timeout(1)]
+    fn rmt_loopback() {
+        let peripherals = Peripherals::take();
+        let system = SystemControl::new(peripherals.SYSTEM);
+        let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
+
+        let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
+
+        cfg_if::cfg_if! {
+            if #[cfg(feature = "esp32h2")] {
+                let freq = 32.MHz();
+            } else {
+                let freq = 80.MHz();
+            }
+        };
+
+        let rmt = Rmt::new(peripherals.RMT, freq, &clocks, None).unwrap();
+
+        let tx_config = TxChannelConfig {
+            clk_divider: 255,
+            ..TxChannelConfig::default()
+        };
+
+        let tx_channel = {
+            use esp_hal::rmt::TxChannelCreator;
+            rmt.channel0.configure(io.pins.gpio2, tx_config).unwrap()
+        };
+
+        let rx_config = RxChannelConfig {
+            clk_divider: 255,
+            idle_threshold: 1000,
+            ..RxChannelConfig::default()
+        };
+
+        cfg_if::cfg_if! {
+            if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
+                let  rx_channel = {
+                    use esp_hal::rmt::RxChannelCreator;
+                    rmt.channel1.configure(io.pins.gpio4, rx_config).unwrap()
+                };
+            } else if #[cfg(feature = "esp32s3")] {
+                let  rx_channel = {
+                    use esp_hal::rmt::RxChannelCreator;
+                    rmt.channel7.configure(io.pins.gpio4, rx_config).unwrap()
+                };
+            } else {
+                let  rx_channel = {
+                    use esp_hal::rmt::RxChannelCreator;
+                    rmt.channel2.configure(io.pins.gpio4, rx_config).unwrap()
+                };
+            }
+        }
+
+        let mut tx_data = [PulseCode {
+            level1: true,
+            length1: 200,
+            level2: false,
+            length2: 50,
+        }; 20];
+
+        tx_data[tx_data.len() - 2] = PulseCode {
+            level1: true,
+            length1: 3000,
+            level2: false,
+            length2: 500,
+        };
+        tx_data[tx_data.len() - 1] = PulseCode::default();
+
+        let mut rcv_data = [PulseCode {
+            level1: false,
+            length1: 0,
+            level2: false,
+            length2: 0,
+        }; 20];
+
+        let rx_transaction = rx_channel.receive(&mut rcv_data).unwrap();
+        let tx_transaction = tx_channel.transmit(&tx_data);
+        tx_transaction.wait().unwrap();
+        rx_transaction.wait().unwrap();
+
+        // the last two pulse-codes are the ones which wait for the timeout so they
+        // can't be equal
+        assert_eq!(&tx_data[..18], &rcv_data[..18]);
+    }
+}