diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs index 83c422cb3..6eff6b056 100644 --- a/esp-hal/src/dma/gdma.rs +++ b/esp-hal/src/dma/gdma.rs @@ -752,10 +752,10 @@ mod m2m { 64 => DmaExtMemBKSize::Size64, _ => panic!("unsupported cache line size"), }; - if crate::soc::is_valid_psram_address(tx_ptr as u32) { + if crate::soc::is_valid_psram_address(tx_ptr as usize) { self.channel.tx.set_ext_mem_block_size(align); } - if crate::soc::is_valid_psram_address(rx_ptr as u32) { + if crate::soc::is_valid_psram_address(rx_ptr as usize) { self.channel.rx.set_ext_mem_block_size(align); } } diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs index bc84d401c..ab6839e69 100644 --- a/esp-hal/src/dma/mod.rs +++ b/esp-hal/src/dma/mod.rs @@ -944,10 +944,10 @@ impl DescriptorChain { data: *mut u8, len: usize, ) -> Result<(), DmaError> { - if !crate::soc::is_valid_ram_address(self.first() as u32) - || !crate::soc::is_valid_ram_address(self.last() as u32) - || !crate::soc::is_valid_memory_address(data as u32) - || !crate::soc::is_valid_memory_address(unsafe { data.add(len) } as u32) + if !crate::soc::is_valid_ram_address(self.first() as usize) + || !crate::soc::is_valid_ram_address(self.last() as usize) + || !crate::soc::is_valid_memory_address(data as usize) + || !crate::soc::is_valid_memory_address(unsafe { data.add(len) } as usize) { return Err(DmaError::UnsupportedMemoryRegion); } @@ -1016,10 +1016,10 @@ impl DescriptorChain { data: *const u8, len: usize, ) -> Result<(), DmaError> { - if !crate::soc::is_valid_ram_address(self.first() as u32) - || !crate::soc::is_valid_ram_address(self.last() as u32) - || !crate::soc::is_valid_memory_address(data as u32) - || !crate::soc::is_valid_memory_address(unsafe { data.add(len) } as u32) + if !crate::soc::is_valid_ram_address(self.first() as usize) + || !crate::soc::is_valid_ram_address(self.last() as usize) + || !crate::soc::is_valid_memory_address(data as usize) + || !crate::soc::is_valid_memory_address(unsafe { data.add(len) } as usize) { return Err(DmaError::UnsupportedMemoryRegion); } @@ -1522,7 +1522,7 @@ where // we are forcing the DMA alignment to the cache line size // required when we are using dcache let alignment = crate::soc::cache_get_dcache_line_size() as usize; - if crate::soc::is_valid_psram_address(des.buffer as u32) { + if crate::soc::is_valid_psram_address(des.buffer as usize) { // both the size and address of the buffer must be aligned if des.buffer as usize % alignment != 0 && des.size() % alignment != 0 { return Err(DmaError::InvalidAlignment); @@ -1760,7 +1760,7 @@ where // we are forcing the DMA alignment to the cache line size // required when we are using dcache let alignment = crate::soc::cache_get_dcache_line_size() as usize; - if crate::soc::is_valid_psram_address(des.buffer as u32) { + if crate::soc::is_valid_psram_address(des.buffer as usize) { // both the size and address of the buffer must be aligned if des.buffer as usize % alignment != 0 && des.size() % alignment != 0 { return Err(DmaError::InvalidAlignment); @@ -2246,7 +2246,7 @@ unsafe impl DmaTxBuffer for DmaTxBuf { } #[cfg(esp32s3)] - if crate::soc::is_valid_psram_address(self.buffer.as_ptr() as u32) { + if crate::soc::is_valid_psram_address(self.buffer.as_ptr() as usize) { unsafe { crate::soc::cache_writeback_addr( self.buffer.as_ptr() as u32, diff --git a/esp-hal/src/soc/esp32/mod.rs b/esp-hal/src/soc/esp32/mod.rs index 5f7e9311e..9777ca5f5 100644 --- a/esp-hal/src/soc/esp32/mod.rs +++ b/esp-hal/src/soc/esp32/mod.rs @@ -38,9 +38,9 @@ pub(crate) mod constants { /// The size, in bytes, of each RMT channel's dedicated RAM. pub const RMT_CHANNEL_RAM_SIZE: usize = 64; /// The lower bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_LOW: u32 = 0x3FFA_E000; + pub const SOC_DRAM_LOW: usize = 0x3FFA_E000; /// The upper bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_HIGH: u32 = 0x4000_0000; + pub const SOC_DRAM_HIGH: usize = 0x4000_0000; /// A reference clock tick of 1 MHz. pub const REF_TICK: fugit::HertzU32 = fugit::HertzU32::MHz(1); } diff --git a/esp-hal/src/soc/esp32c2/mod.rs b/esp-hal/src/soc/esp32c2/mod.rs index 32717ba8b..f479a7e76 100644 --- a/esp-hal/src/soc/esp32c2/mod.rs +++ b/esp-hal/src/soc/esp32c2/mod.rs @@ -28,9 +28,9 @@ pub(crate) mod registers { pub(crate) mod constants { /// The lower bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_LOW: u32 = 0x3FCA_0000; + pub const SOC_DRAM_LOW: usize = 0x3FCA_0000; /// The upper bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_HIGH: u32 = 0x3FCE_0000; + pub const SOC_DRAM_HIGH: usize = 0x3FCE_0000; /// RC FAST Clock value (Hertz). pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500); diff --git a/esp-hal/src/soc/esp32c3/mod.rs b/esp-hal/src/soc/esp32c3/mod.rs index 2d45d4e47..0b3d43f1b 100644 --- a/esp-hal/src/soc/esp32c3/mod.rs +++ b/esp-hal/src/soc/esp32c3/mod.rs @@ -42,13 +42,13 @@ pub(crate) mod constants { pub const RMT_CHANNEL_RAM_SIZE: usize = 48; /// RMT Clock source value. pub const RMT_CLOCK_SRC: u8 = 1; - /// RMT Clock source frequence. + /// RMT Clock source frequency. pub const RMT_CLOCK_SRC_FREQ: fugit::HertzU32 = fugit::HertzU32::MHz(80); /// The lower bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_LOW: u32 = 0x3FC8_0000; + pub const SOC_DRAM_LOW: usize = 0x3FC8_0000; /// The upper bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_HIGH: u32 = 0x3FCE_0000; + pub const SOC_DRAM_HIGH: usize = 0x3FCE_0000; /// RC FAST Clock value (Hertz). pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500); diff --git a/esp-hal/src/soc/esp32c6/mod.rs b/esp-hal/src/soc/esp32c6/mod.rs index 01e80a953..461b5e551 100644 --- a/esp-hal/src/soc/esp32c6/mod.rs +++ b/esp-hal/src/soc/esp32c6/mod.rs @@ -54,9 +54,9 @@ pub(crate) mod constants { pub const PARL_IO_SCLK: u32 = 240_000_000; /// The lower address boundary for system DRAM. - pub const SOC_DRAM_LOW: u32 = 0x4080_0000; + pub const SOC_DRAM_LOW: usize = 0x4080_0000; /// The upper address boundary for system DRAM. - pub const SOC_DRAM_HIGH: u32 = 0x4088_0000; + pub const SOC_DRAM_HIGH: usize = 0x4088_0000; /// RC FAST Clock value (Hertz). pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17_500); diff --git a/esp-hal/src/soc/esp32h2/mod.rs b/esp-hal/src/soc/esp32h2/mod.rs index 8ebcaadee..d87720b42 100644 --- a/esp-hal/src/soc/esp32h2/mod.rs +++ b/esp-hal/src/soc/esp32h2/mod.rs @@ -54,9 +54,9 @@ pub(crate) mod constants { pub const PARL_IO_SCLK: u32 = 96_000_000; /// Start address of the system's DRAM (low range). - pub const SOC_DRAM_LOW: u32 = 0x4080_0000; + pub const SOC_DRAM_LOW: usize = 0x4080_0000; /// End address of the system's DRAM (high range). - pub const SOC_DRAM_HIGH: u32 = 0x4085_0000; + pub const SOC_DRAM_HIGH: usize = 0x4085_0000; /// RC FAST Clock value (Hertz). pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500); diff --git a/esp-hal/src/soc/esp32s2/mod.rs b/esp-hal/src/soc/esp32s2/mod.rs index f2edb5aac..0f6f02447 100644 --- a/esp-hal/src/soc/esp32s2/mod.rs +++ b/esp-hal/src/soc/esp32s2/mod.rs @@ -43,9 +43,9 @@ pub(crate) mod constants { /// Size of the RAM allocated per RMT channel, in bytes. pub const RMT_CHANNEL_RAM_SIZE: usize = 64; /// Start address of the system's DRAM (low range). - pub const SOC_DRAM_LOW: u32 = 0x3FFB_0000; + pub const SOC_DRAM_LOW: usize = 0x3FFB_0000; /// End address of the system's DRAM (high range). - pub const SOC_DRAM_HIGH: u32 = 0x4000_0000; + pub const SOC_DRAM_HIGH: usize = 0x4000_0000; /// Reference clock tick frequency, set to 1 MHz. pub const REF_TICK: fugit::HertzU32 = fugit::HertzU32::MHz(1); } diff --git a/esp-hal/src/soc/esp32s3/mod.rs b/esp-hal/src/soc/esp32s3/mod.rs index dde09d9df..9d5fdf955 100644 --- a/esp-hal/src/soc/esp32s3/mod.rs +++ b/esp-hal/src/soc/esp32s3/mod.rs @@ -46,13 +46,13 @@ pub(crate) mod constants { pub const RMT_CHANNEL_RAM_SIZE: usize = 48; /// RMT Clock source value. pub const RMT_CLOCK_SRC: u8 = 1; - /// RMT Clock source frequence. + /// RMT Clock source frequency. pub const RMT_CLOCK_SRC_FREQ: fugit::HertzU32 = fugit::HertzU32::MHz(80); /// The lower bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_LOW: u32 = 0x3FC8_8000; + pub const SOC_DRAM_LOW: usize = 0x3FC8_8000; /// The upper bound of the system's DRAM (Data RAM) address space. - pub const SOC_DRAM_HIGH: u32 = 0x3FD0_0000; + pub const SOC_DRAM_HIGH: usize = 0x3FD0_0000; /// A reference clock tick of 1 MHz. pub const RC_FAST_CLK: fugit::HertzU32 = fugit::HertzU32::kHz(17500); diff --git a/esp-hal/src/soc/mod.rs b/esp-hal/src/soc/mod.rs index b0cf18de8..67f068643 100644 --- a/esp-hal/src/soc/mod.rs +++ b/esp-hal/src/soc/mod.rs @@ -1,3 +1,5 @@ +use core::ops::Range; + use portable_atomic::{AtomicU8, Ordering}; pub use self::implementation::*; @@ -21,6 +23,18 @@ mod psram_common; #[cfg(psram)] static MAPPED_PSRAM: Locked = Locked::new(MappedPsram { memory_range: 0..0 }); +fn psram_range() -> Range { + cfg_if::cfg_if! { + if #[cfg(psram)] { + MAPPED_PSRAM.with(|mapped_psram| mapped_psram.memory_range.clone()) + } else { + 0..0 + } + } +} + +const DRAM: Range = self::constants::SOC_DRAM_LOW..self::constants::SOC_DRAM_HIGH; + #[cfg(psram)] pub struct MappedPsram { memory_range: core::ops::Range, @@ -83,36 +97,40 @@ impl self::efuse::Efuse { } #[allow(unused)] -pub(crate) fn is_valid_ram_address(address: u32) -> bool { - (self::constants::SOC_DRAM_LOW..=self::constants::SOC_DRAM_HIGH).contains(&address) +pub(crate) fn is_valid_ram_address(address: usize) -> bool { + addr_in_range(address, DRAM) } #[allow(unused)] pub(crate) fn is_slice_in_dram(slice: &[T]) -> bool { - let start = slice.as_ptr() as u32; - let end = start + slice.len() as u32; - self::constants::SOC_DRAM_LOW <= start && end <= self::constants::SOC_DRAM_HIGH + slice_in_range(slice, DRAM) } #[allow(unused)] -pub(crate) fn is_valid_psram_address(address: u32) -> bool { - #[cfg(psram)] - { - let memory_range = MAPPED_PSRAM.with(|mapped_psram| mapped_psram.memory_range.clone()); - memory_range.contains(&(address as usize)) - } - #[cfg(not(psram))] - false +pub(crate) fn is_valid_psram_address(address: usize) -> bool { + addr_in_range(address, psram_range()) } #[allow(unused)] pub(crate) fn is_slice_in_psram(slice: &[T]) -> bool { - let start = slice.as_ptr() as u32; - let end = start + slice.len() as u32; - is_valid_psram_address(start) && is_valid_psram_address(end) + slice_in_range(slice, psram_range()) } #[allow(unused)] -pub(crate) fn is_valid_memory_address(address: u32) -> bool { +pub(crate) fn is_valid_memory_address(address: usize) -> bool { is_valid_ram_address(address) || is_valid_psram_address(address) } + +fn slice_in_range(slice: &[T], range: Range) -> bool { + let slice = slice.as_ptr_range(); + let start = slice.start as usize; + let end = slice.end as usize; + // `end` is >= `start`, so we don't need to check that `end > range.start` + // `end` is also one past the last element, so it can be equal to the range's + // end which is also one past the memory region's last valid address. + addr_in_range(start, range.clone()) && end <= range.end +} + +fn addr_in_range(addr: usize, range: Range) -> bool { + range.contains(&addr) +}