From e745e84869fedc8853241039e4fc36e360367d2a Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 5 May 2022 11:45:48 +0200 Subject: [PATCH] Fix a whole bunch of clippy warnings --- esp-hal-common/src/gpio.rs | 20 ++++---- esp-hal-common/src/i2c.rs | 67 ++++++++++++-------------- esp-hal-common/src/interrupt/riscv.rs | 6 +-- esp-hal-common/src/interrupt/xtensa.rs | 30 ++++++------ esp-hal-common/src/serial.rs | 4 +- esp-hal-common/src/spi.rs | 17 +++---- esp-hal-common/src/timer.rs | 4 +- 7 files changed, 67 insertions(+), 81 deletions(-) diff --git a/esp-hal-common/src/gpio.rs b/esp-hal-common/src/gpio.rs index b0485a9f6..7564d7356 100644 --- a/esp-hal-common/src/gpio.rs +++ b/esp-hal-common/src/gpio.rs @@ -107,13 +107,13 @@ pub trait Pin { fn clear_interrupt(&mut self); - fn is_pcore_interrupt_set(&mut self) -> bool; + fn is_pcore_interrupt_set(&self) -> bool; - fn is_pcore_non_maskable_interrupt_set(&mut self) -> bool; + fn is_pcore_non_maskable_interrupt_set(&self) -> bool; - fn is_acore_interrupt_set(&mut self) -> bool; + fn is_acore_interrupt_set(&self) -> bool; - fn is_acore_non_maskable_interrupt_set(&mut self) -> bool; + fn is_acore_non_maskable_interrupt_set(&self) -> bool; fn enable_hold(&mut self, on: bool); } @@ -127,7 +127,7 @@ pub trait InputPin: Pin { fn enable_input_in_sleep_mode(&mut self, on: bool) -> &mut Self; - fn is_input_high(&mut self) -> bool; + fn is_input_high(&self) -> bool; fn connect_input_to_peripheral(&mut self, signal: Self::InputSignal) -> &mut Self { self.connect_input_to_peripheral_with_options(signal, false, false) @@ -330,7 +330,7 @@ macro_rules! impl_input { self } - fn is_input_high(&mut self) -> bool { + fn is_input_high(&self) -> bool { unsafe { &*GPIO::ptr() }.$reg.read().$reader().bits() & (1 << $bit) != 0 } @@ -425,19 +425,19 @@ macro_rules! impl_input { unsafe {w.bits(1 << $bit)}) } - fn is_pcore_interrupt_set(&mut self) -> bool { + fn is_pcore_interrupt_set(&self) -> bool { (unsafe {&*GPIO::ptr()}.$pcpu_int.read().bits() & (1 << $bit)) !=0 } - fn is_pcore_non_maskable_interrupt_set(&mut self) -> bool { + fn is_pcore_non_maskable_interrupt_set(&self) -> bool { (unsafe {&*GPIO::ptr()}.$pcpu_nmi.read().bits() & (1 << $bit)) !=0 } - fn is_acore_interrupt_set(&mut self) -> bool { + fn is_acore_interrupt_set(&self) -> bool { (unsafe {&*GPIO::ptr()}.$acpu_int.read().bits() & (1 << $bit)) !=0 } - fn is_acore_non_maskable_interrupt_set(&mut self) -> bool { + fn is_acore_non_maskable_interrupt_set(&self) -> bool { (unsafe {&*GPIO::ptr()}.$acpu_nmi.read().bits() & (1 << $bit)) !=0 } diff --git a/esp-hal-common/src/i2c.rs b/esp-hal-common/src/i2c.rs index 6265058f6..181ca6754 100644 --- a/esp-hal-common/src/i2c.rs +++ b/esp-hal-common/src/i2c.rs @@ -75,10 +75,10 @@ enum Command { impl From for u16 { fn from(c: Command) -> u16 { let opcode = match c { - Command::Start => Opcode::RSTART, - Command::Stop => Opcode::STOP, - Command::Write { .. } => Opcode::WRITE, - Command::Read { .. } => Opcode::READ, + Command::Start => Opcode::RStart, + Command::Stop => Opcode::Stop, + Command::Write { .. } => Opcode::Write, + Command::Read { .. } => Opcode::Read, }; let length = match c { @@ -87,7 +87,7 @@ impl From for u16 { }; let ack_exp = match c { - Command::Start | Command::Stop | Command::Read { .. } => Ack::NACK, + Command::Start | Command::Stop | Command::Read { .. } => Ack::Nack, Command::Write { ack_exp: exp, .. } => exp, }; @@ -99,7 +99,7 @@ impl From for u16 { }; let ack_value = match c { - Command::Start | Command::Stop | Command::Write { .. } => Ack::NACK, + Command::Start | Command::Stop | Command::Write { .. } => Ack::Nack, Command::Read { ack_value: ack, .. } => ack, }; @@ -111,13 +111,13 @@ impl From for u16 { cmd &= !(1 << 8); } - if ack_exp == Ack::NACK { + if ack_exp == Ack::Nack { cmd |= 1 << 9; } else { cmd &= !(1 << 9); } - if ack_value == Ack::NACK { + if ack_value == Ack::Nack { cmd |= 1 << 10; } else { cmd &= !(1 << 10); @@ -130,30 +130,30 @@ impl From for u16 { } enum OperationType { - WRITE = 0, - READ = 1, + Write = 0, + Read = 1, } #[derive(Eq, PartialEq, Copy, Clone)] enum Ack { - ACK, - NACK, + Ack, + Nack, } #[cfg(any(feature = "esp32c3", feature = "esp32s3"))] enum Opcode { - RSTART = 6, - WRITE = 1, - READ = 3, - STOP = 2, + RStart = 6, + Write = 1, + Read = 3, + Stop = 2, } #[cfg(any(feature = "esp32", feature = "esp32s2"))] enum Opcode { - RSTART = 0, - WRITE = 1, - READ = 2, - STOP = 3, + RStart = 0, + Write = 1, + Read = 2, + Stop = 3, } /// I2C peripheral container (I2C) @@ -454,29 +454,24 @@ pub trait Instance { let scl_high: u16 = half_cycle - scl_wait_high as u16; let sda_hold = half_cycle / 4; let sda_sample = scl_high / 2; - } - else if #[cfg(feature = "esp32s3")] { + } else if #[cfg(feature = "esp32s3")] { let scl_high = if bus_freq <= 50000 { half_cycle } else { half_cycle / 5 * 4 + 4 }; let scl_wait_high: u8 = (half_cycle - scl_high).try_into().map_err(|_| SetupError::InvalidClkConfig)?; let sda_hold = half_cycle / 2; let sda_sample = half_cycle / 2; - } - else if #[cfg(feature = "esp32s2")] { + } else if #[cfg(feature = "esp32s2")] { let scl_high = half_cycle / 2 + 2; let scl_wait_high = scl_high - (scl_high/2 +2) + 4; // NOTE the additional +4 compared to ESP-IDF let sda_hold = half_cycle / 2; let sda_sample = scl_high / 2 - 1; - } - else { + } else { // ESP32 is default (as it is the simplest case and does not even have // the wait_high field) let scl_high = half_cycle; let sda_hold = half_cycle / 2; let sda_sample = scl_high / 2; - let tout: u16 = (half_cycle * 20) - .try_into() - .map_err(|_| SetupError::InvalidClkConfig)?; - } + let tout: u16 = half_cycle * 20; + } } let scl_low = half_cycle; @@ -654,7 +649,7 @@ pub trait Instance { // Load address and R/W bit into FIFO write_fifo( self.register_block(), - addr << 1 | OperationType::WRITE as u8, + addr << 1 | OperationType::Write as u8, ); // Load actual data bytes for byte in bytes { @@ -668,7 +663,7 @@ pub trait Instance { cmd_write.write(|w| unsafe { w.command().bits( Command::Write { - ack_exp: Ack::ACK, + ack_exp: Ack::Ack, ack_check_en: true, length: 1 + bytes.len() as u8, } @@ -704,7 +699,7 @@ pub trait Instance { .write(|w| unsafe { w.command().bits(Command::Start.into()) }); // Load address and R/W bit into FIFO - write_fifo(self.register_block(), addr << 1 | OperationType::READ as u8); + write_fifo(self.register_block(), addr << 1 | OperationType::Read as u8); // Check if we have another cmd register ready, otherwise return appropriate // error @@ -714,7 +709,7 @@ pub trait Instance { .write(|w| unsafe { w.command().bits( Command::Write { - ack_exp: Ack::ACK, + ack_exp: Ack::Ack, ack_check_en: true, length: 1, } @@ -732,7 +727,7 @@ pub trait Instance { .write(|w| unsafe { w.command().bits( Command::Read { - ack_value: Ack::ACK, + ack_value: Ack::Ack, length: buffer.len() as u8 - 1, } .into(), @@ -747,7 +742,7 @@ pub trait Instance { .write(|w| unsafe { w.command().bits( Command::Read { - ack_value: Ack::NACK, + ack_value: Ack::Nack, length: 1, } .into(), diff --git a/esp-hal-common/src/interrupt/riscv.rs b/esp-hal-common/src/interrupt/riscv.rs index f8c0af5a7..2d1edd2e6 100644 --- a/esp-hal-common/src/interrupt/riscv.rs +++ b/esp-hal-common/src/interrupt/riscv.rs @@ -289,11 +289,7 @@ pub unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) { #[doc(hidden)] unsafe fn handle_exception(pc: usize, trap_frame: *mut TrapFrame) { let insn: usize = *(pc as *const _); - let needs_atomic_emulation = if (insn & 0b1111111) != 0b0101111 { - false - } else { - true - }; + let needs_atomic_emulation = (insn & 0b1111111) == 0b0101111; if !needs_atomic_emulation { extern "C" { diff --git a/esp-hal-common/src/interrupt/xtensa.rs b/esp-hal-common/src/interrupt/xtensa.rs index eba0f7e6d..b44ac6390 100644 --- a/esp-hal-common/src/interrupt/xtensa.rs +++ b/esp-hal-common/src/interrupt/xtensa.rs @@ -57,11 +57,11 @@ pub fn enable(core: Cpu, interrupt: Interrupt, which: CpuInterrupt) { let interrupt_number = interrupt as isize; let cpu_interrupt_number = which as isize; let intr_map_base = match core { - Cpu::ProCpu => (&*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), + Cpu::ProCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), #[cfg(feature = "dual_core")] - Cpu::AppCpu => (&*core1_interrupt_peripheral()).app_mac_intr_map.as_ptr(), + Cpu::AppCpu => (*core1_interrupt_peripheral()).app_mac_intr_map.as_ptr(), #[cfg(feature = "single_core")] - Cpu::AppCpu => (&*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), + Cpu::AppCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), }; intr_map_base .offset(interrupt_number) @@ -74,11 +74,11 @@ pub fn disable(core: Cpu, interrupt: Interrupt) { unsafe { let interrupt_number = interrupt as isize; let intr_map_base = match core { - Cpu::ProCpu => (&*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), + Cpu::ProCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), #[cfg(feature = "dual_core")] - Cpu::AppCpu => (&*core1_interrupt_peripheral()).app_mac_intr_map.as_ptr(), + Cpu::AppCpu => (*core1_interrupt_peripheral()).app_mac_intr_map.as_ptr(), #[cfg(feature = "single_core")] - Cpu::AppCpu => (&*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), + Cpu::AppCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map.as_ptr(), }; intr_map_base.offset(interrupt_number).write_volatile(0); } @@ -96,16 +96,16 @@ pub fn get_status(core: Cpu) -> u128 { unsafe { match core { Cpu::ProCpu => { - ((&*core0_interrupt_peripheral()) + ((*core0_interrupt_peripheral()) .pro_intr_status_0 .read() .bits() as u128) - | ((&*core0_interrupt_peripheral()) + | ((*core0_interrupt_peripheral()) .pro_intr_status_1 .read() .bits() as u128) << 32 - | ((&*core0_interrupt_peripheral()) + | ((*core0_interrupt_peripheral()) .pro_intr_status_2 .read() .bits() as u128) @@ -113,16 +113,16 @@ pub fn get_status(core: Cpu) -> u128 { } #[cfg(feature = "dual_core")] Cpu::AppCpu => { - ((&*core1_interrupt_peripheral()) + ((*core1_interrupt_peripheral()) .app_intr_status_0 .read() .bits() as u128) - | ((&*core1_interrupt_peripheral()) + | ((*core1_interrupt_peripheral()) .app_intr_status_1 .read() .bits() as u128) << 32 - | ((&*core1_interrupt_peripheral()) + | ((*core1_interrupt_peripheral()) .app_intr_status_2 .read() .bits() as u128) @@ -130,16 +130,16 @@ pub fn get_status(core: Cpu) -> u128 { } #[cfg(feature = "single_core")] Cpu::AppCpu => { - ((&*core0_interrupt_peripheral()) + ((*core0_interrupt_peripheral()) .pro_intr_status_0 .read() .bits() as u128) - | ((&*core0_interrupt_peripheral()) + | ((*core0_interrupt_peripheral()) .pro_intr_status_1 .read() .bits() as u128) << 32 - | ((&*core0_interrupt_peripheral()) + | ((*core0_interrupt_peripheral()) .pro_intr_status_2 .read() .bits() as u128) diff --git a/esp-hal-common/src/serial.rs b/esp-hal-common/src/serial.rs index 3169fd2e6..5107534c0 100644 --- a/esp-hal-common/src/serial.rs +++ b/esp-hal-common/src/serial.rs @@ -104,7 +104,7 @@ pub trait Instance { .into() } - fn is_tx_idle(&mut self) -> bool { + fn is_tx_idle(&self) -> bool { #[cfg(feature = "esp32")] let idle = self.register_block().status.read().st_utx_out().bits() == 0x0u8; #[cfg(not(feature = "esp32"))] @@ -113,7 +113,7 @@ pub trait Instance { idle } - fn is_rx_idle(&mut self) -> bool { + fn is_rx_idle(&self) -> bool { #[cfg(feature = "esp32")] let idle = self.register_block().status.read().st_urx_out().bits() == 0x0u8; #[cfg(not(feature = "esp32"))] diff --git a/esp-hal-common/src/spi.rs b/esp-hal-common/src/spi.rs index 2db8cd10b..be6b03132 100644 --- a/esp-hal-common/src/spi.rs +++ b/esp-hal-common/src/spi.rs @@ -75,10 +75,8 @@ where spi.enable_peripheral(system); - let mut spi = Self { spi: spi }; - + let mut spi = Self { spi }; spi.spi.setup(frequency); - spi.spi.init(); spi.spi.set_data_mode(mode); @@ -207,9 +205,6 @@ pub trait Instance { */ let mut pre: i32; - let n: i32; - let mut h: i32; - let l: i32; let mut bestn: i32 = -1; let mut bestpre: i32 = -1; let mut besterr: i32 = 0; @@ -242,20 +237,20 @@ pub trait Instance { } } - n = bestn; + let n: i32 = bestn; pre = bestpre as i32; - l = n; + let l: i32 = n; /* Effectively, this does: * h = round((duty_cycle * n) / 256) */ - h = (duty_cycle * n + 127) / 256; + let mut h: i32 = (duty_cycle * n + 127) / 256; if h <= 0 { h = 1; } - reg_val = ((l as u32 - 1) << 0) | + reg_val = (l as u32 - 1) | ((h as u32 - 1) << 6) | ((n as u32 - 1) << 12) | ((pre as u32 - 1) << 18); @@ -353,7 +348,7 @@ pub trait Instance { let mut fifo_ptr = reg_block.w0.as_ptr(); for chunk in chunk.chunks(4) { let mut u32_as_bytes = [0u8; 4]; - u32_as_bytes[0..(chunk.len())].clone_from_slice(&chunk); + u32_as_bytes[0..(chunk.len())].clone_from_slice(chunk); let reg_val: u32 = u32::from_le_bytes(u32_as_bytes); unsafe { diff --git a/esp-hal-common/src/timer.rs b/esp-hal-common/src/timer.rs index 600775766..f0c2b63a5 100644 --- a/esp-hal-common/src/timer.rs +++ b/esp-hal-common/src/timer.rs @@ -73,7 +73,7 @@ pub trait Instance { .modify(|_, w| w.t0_en().bit(state)); } - fn is_counter_active(&mut self) -> bool { + fn is_counter_active(&self) -> bool { self.register_block().t0config.read().t0_en().bit_is_set() } @@ -95,7 +95,7 @@ pub trait Instance { .modify(|_, w| w.t0_alarm_en().bit(state)); } - fn is_alarm_active(&mut self) -> bool { + fn is_alarm_active(&self) -> bool { self.register_block() .t0config .read()