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Clean up (#2266)

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Dániel Buga 2024-10-03 09:02:34 +02:00 committed by GitHub
parent 30aef580e3
commit e033162ffd
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GPG Key ID: B5690EEEBB952194
1 changed files with 93 additions and 161 deletions
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254
esp-hal/src/spi/slave.rs
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@ -243,7 +243,7 @@ pub mod dma {
impl<'d, T, C, DmaMode> DmaSupport for SpiDma<'d, T, C, DmaMode> impl<'d, T, C, DmaMode> DmaSupport for SpiDma<'d, T, C, DmaMode>
where where
T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>, T: InstanceDma,
C: DmaChannel, C: DmaChannel,
C::P: SpiPeripheral, C::P: SpiPeripheral,
DmaMode: Mode, DmaMode: Mode,
@ -264,7 +264,7 @@ pub mod dma {
impl<'d, T, C, DmaMode> DmaSupportTx for SpiDma<'d, T, C, DmaMode> impl<'d, T, C, DmaMode> DmaSupportTx for SpiDma<'d, T, C, DmaMode>
where where
T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>, T: InstanceDma,
C: DmaChannel, C: DmaChannel,
C::P: SpiPeripheral, C::P: SpiPeripheral,
DmaMode: Mode, DmaMode: Mode,
@ -282,7 +282,7 @@ pub mod dma {
impl<'d, T, C, DmaMode> DmaSupportRx for SpiDma<'d, T, C, DmaMode> impl<'d, T, C, DmaMode> DmaSupportRx for SpiDma<'d, T, C, DmaMode>
where where
T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>, T: InstanceDma,
C: DmaChannel, C: DmaChannel,
C::P: SpiPeripheral, C::P: SpiPeripheral,
DmaMode: Mode, DmaMode: Mode,
@ -300,7 +300,7 @@ pub mod dma {
impl<'d, T, C, DmaMode> SpiDma<'d, T, C, DmaMode> impl<'d, T, C, DmaMode> SpiDma<'d, T, C, DmaMode>
where where
T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>, T: InstanceDma,
C: DmaChannel, C: DmaChannel,
C::P: SpiPeripheral, C::P: SpiPeripheral,
DmaMode: Mode, DmaMode: Mode,
@ -399,13 +399,11 @@ pub mod dma {
} }
#[doc(hidden)] #[doc(hidden)]
pub trait InstanceDma<RX, TX>: Instance pub trait InstanceDma: Instance {
where fn dma_peripheral(&self) -> DmaPeripheral;
RX: Rx,
TX: Tx,
{
#[allow(clippy::too_many_arguments)] #[allow(clippy::too_many_arguments)]
unsafe fn start_transfer_dma( unsafe fn start_transfer_dma<RX, TX>(
&mut self, &mut self,
rx_chain: &mut DescriptorChain, rx_chain: &mut DescriptorChain,
tx_chain: &mut DescriptorChain, tx_chain: &mut DescriptorChain,
@ -415,7 +413,11 @@ where
write_buffer_len: usize, write_buffer_len: usize,
rx: &mut RX, rx: &mut RX,
tx: &mut TX, tx: &mut TX,
) -> Result<(), Error> { ) -> Result<(), Error>
where
RX: Rx,
TX: Tx,
{
let reg_block = self.register_block(); let reg_block = self.register_block();
rx.is_done(); rx.is_done();
@ -447,13 +449,16 @@ where
Ok(()) Ok(())
} }
unsafe fn start_write_bytes_dma( unsafe fn start_write_bytes_dma<TX>(
&mut self, &mut self,
tx_chain: &mut DescriptorChain, tx_chain: &mut DescriptorChain,
ptr: *const u8, ptr: *const u8,
len: usize, len: usize,
tx: &mut TX, tx: &mut TX,
) -> Result<(), Error> { ) -> Result<(), Error>
where
TX: Tx,
{
let reg_block = self.register_block(); let reg_block = self.register_block();
tx.is_done(); tx.is_done();
@ -480,13 +485,16 @@ where
Ok(()) Ok(())
} }
unsafe fn start_read_bytes_dma( unsafe fn start_read_bytes_dma<RX>(
&mut self, &mut self,
rx_chain: &mut DescriptorChain, rx_chain: &mut DescriptorChain,
ptr: *mut u8, ptr: *mut u8,
len: usize, len: usize,
rx: &mut RX, rx: &mut RX,
) -> Result<(), Error> { ) -> Result<(), Error>
where
RX: Rx,
{
let reg_block = self.register_block(); let reg_block = self.register_block();
rx.is_done(); rx.is_done();
@ -512,25 +520,13 @@ where
Ok(()) Ok(())
} }
fn dma_peripheral(&self) -> DmaPeripheral {
match self.spi_num() {
2 => DmaPeripheral::Spi2,
#[cfg(spi3)]
3 => DmaPeripheral::Spi3,
_ => panic!("Illegal SPI instance"),
}
}
#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] #[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
fn enable_dma(&self) { fn enable_dma(&self) {
let reg_block = self.register_block(); let reg_block = self.register_block();
reg_block.dma_conf().modify(|_, w| { reg_block.dma_conf().modify(|_, w| {
w.dma_tx_ena() w.dma_tx_ena().set_bit();
.set_bit() w.dma_rx_ena().set_bit();
.dma_rx_ena() w.rx_eof_en().clear_bit()
.set_bit()
.rx_eof_en()
.clear_bit()
}); });
} }
@ -543,16 +539,11 @@ where
fn clear_dma_interrupts(&self) { fn clear_dma_interrupts(&self) {
let reg_block = self.register_block(); let reg_block = self.register_block();
reg_block.dma_int_clr().write(|w| { reg_block.dma_int_clr().write(|w| {
w.dma_infifo_full_err() w.dma_infifo_full_err().clear_bit_by_one();
.clear_bit_by_one() w.dma_outfifo_empty_err().clear_bit_by_one();
.dma_outfifo_empty_err() w.trans_done().clear_bit_by_one();
.clear_bit_by_one() w.mst_rx_afifo_wfull_err().clear_bit_by_one();
.trans_done() w.mst_tx_afifo_rempty_err().clear_bit_by_one()
.clear_bit_by_one()
.mst_rx_afifo_wfull_err()
.clear_bit_by_one()
.mst_tx_afifo_rempty_err()
.clear_bit_by_one()
}); });
} }
@ -560,24 +551,15 @@ where
fn clear_dma_interrupts(&self) { fn clear_dma_interrupts(&self) {
let reg_block = self.register_block(); let reg_block = self.register_block();
reg_block.dma_int_clr().write(|w| { reg_block.dma_int_clr().write(|w| {
w.inlink_dscr_empty() w.inlink_dscr_empty().clear_bit_by_one();
.clear_bit_by_one() w.outlink_dscr_error().clear_bit_by_one();
.outlink_dscr_error() w.inlink_dscr_error().clear_bit_by_one();
.clear_bit_by_one() w.in_done().clear_bit_by_one();
.inlink_dscr_error() w.in_err_eof().clear_bit_by_one();
.clear_bit_by_one() w.in_suc_eof().clear_bit_by_one();
.in_done() w.out_done().clear_bit_by_one();
.clear_bit_by_one() w.out_eof().clear_bit_by_one();
.in_err_eof() w.out_total_eof().clear_bit_by_one()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
.out_done()
.clear_bit_by_one()
.out_eof()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
}); });
} }
} }
@ -585,12 +567,9 @@ where
#[cfg(not(esp32s2))] #[cfg(not(esp32s2))]
fn reset_dma_before_usr_cmd(reg_block: &RegisterBlock) { fn reset_dma_before_usr_cmd(reg_block: &RegisterBlock) {
reg_block.dma_conf().modify(|_, w| { reg_block.dma_conf().modify(|_, w| {
w.rx_afifo_rst() w.rx_afifo_rst().set_bit();
.set_bit() w.buf_afifo_rst().set_bit();
.buf_afifo_rst() w.dma_afifo_rst().set_bit()
.set_bit()
.dma_afifo_rst()
.set_bit()
}); });
} }
@ -606,14 +585,10 @@ fn reset_dma_before_load_dma_dscr(_reg_block: &RegisterBlock) {}
#[cfg(esp32s2)] #[cfg(esp32s2)]
fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) { fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
reg_block.dma_conf().modify(|_, w| { reg_block.dma_conf().modify(|_, w| {
w.out_rst() w.out_rst().set_bit();
.set_bit() w.in_rst().set_bit();
.in_rst() w.ahbm_fifo_rst().set_bit();
.set_bit() w.ahbm_rst().set_bit()
.ahbm_fifo_rst()
.set_bit()
.ahbm_rst()
.set_bit()
}); });
#[cfg(esp32s2)] #[cfg(esp32s2)]
@ -622,14 +597,10 @@ fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
.modify(|_, w| w.dma_infifo_full_clr().set_bit()); .modify(|_, w| w.dma_infifo_full_clr().set_bit());
reg_block.dma_conf().modify(|_, w| { reg_block.dma_conf().modify(|_, w| {
w.out_rst() w.out_rst().clear_bit();
.clear_bit() w.in_rst().clear_bit();
.in_rst() w.ahbm_fifo_rst().clear_bit();
.clear_bit() w.ahbm_rst().clear_bit()
.ahbm_fifo_rst()
.clear_bit()
.ahbm_rst()
.clear_bit()
}); });
#[cfg(esp32s2)] #[cfg(esp32s2)]
@ -638,19 +609,16 @@ fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
.modify(|_, w| w.dma_infifo_full_clr().clear_bit()); .modify(|_, w| w.dma_infifo_full_clr().clear_bit());
} }
impl<TX, RX> InstanceDma<RX, TX> for crate::peripherals::SPI2 impl InstanceDma for crate::peripherals::SPI2 {
where fn dma_peripheral(&self) -> DmaPeripheral {
RX: Rx, DmaPeripheral::Spi2
TX: Tx, }
{
} }
#[cfg(spi3)] #[cfg(spi3)]
impl<TX, RX> InstanceDma<RX, TX> for crate::peripherals::SPI3 impl InstanceDma for crate::peripherals::SPI3 {
where fn dma_peripheral(&self) -> DmaPeripheral {
RX: Rx, DmaPeripheral::Spi3
TX: Tx, }
{
} }
#[doc(hidden)] #[doc(hidden)]
@ -680,93 +648,57 @@ pub trait Instance: private::Sealed {
reg_block.slave().write(|w| w.mode().set_bit()); reg_block.slave().write(|w| w.mode().set_bit());
reg_block.user().modify(|_, w| { reg_block.user().modify(|_, w| {
w.usr_miso_highpart() w.usr_miso_highpart().clear_bit();
.clear_bit() w.doutdin().set_bit();
.doutdin() w.usr_miso().clear_bit();
.set_bit() w.usr_mosi().clear_bit();
.usr_miso() w.usr_dummy_idle().clear_bit();
.clear_bit() w.usr_addr().clear_bit();
.usr_mosi() w.usr_command().clear_bit();
.clear_bit() w.sio().clear_bit()
.usr_dummy_idle()
.clear_bit()
.usr_addr()
.clear_bit()
.usr_command()
.clear_bit()
.sio()
.clear_bit()
}); });
#[cfg(not(esp32s2))] #[cfg(not(esp32s2))]
reg_block.clk_gate().modify(|_, w| { reg_block.clk_gate().modify(|_, w| {
w.clk_en() w.clk_en().clear_bit();
.clear_bit() w.mst_clk_active().clear_bit();
.mst_clk_active() w.mst_clk_sel().clear_bit()
.clear_bit()
.mst_clk_sel()
.clear_bit()
}); });
#[cfg(not(esp32s2))]
reg_block.ctrl().modify(|_, w| { reg_block.ctrl().modify(|_, w| {
w.q_pol() w.q_pol().clear_bit();
.clear_bit() w.d_pol().clear_bit();
.d_pol() #[cfg(not(esp32s2))]
.clear_bit() w.hold_pol().clear_bit();
.hold_pol() #[cfg(esp32s2)]
.clear_bit() w.wp().clear_bit();
w
}); });
#[cfg(esp32s2)]
reg_block
.ctrl()
.modify(|_, w| w.q_pol().clear_bit().d_pol().clear_bit().wp().clear_bit());
reg_block.misc().write(|w| unsafe { w.bits(0) }); reg_block.misc().write(|w| unsafe { w.bits(0) });
} }
fn set_data_mode(&mut self, data_mode: SpiMode) -> &mut Self { fn set_data_mode(&mut self, data_mode: SpiMode) -> &mut Self {
let reg_block = self.register_block(); let reg_block = self.register_block();
match data_mode { reg_block.user().modify(|_, w| {
SpiMode::Mode0 => { w.tsck_i_edge()
reg_block .bit(matches!(data_mode, SpiMode::Mode1 | SpiMode::Mode2));
.user() w.rsck_i_edge()
.modify(|_, w| w.tsck_i_edge().clear_bit().rsck_i_edge().clear_bit()); .bit(matches!(data_mode, SpiMode::Mode1 | SpiMode::Mode2))
#[cfg(esp32s2)] });
reg_block.ctrl1().modify(|_, w| w.clk_mode_13().clear_bit()); cfg_if::cfg_if! {
#[cfg(not(esp32s2))] if #[cfg(esp32s2)] {
reg_block.slave().modify(|_, w| w.clk_mode_13().clear_bit()); let ctrl1_reg = reg_block.ctrl1();
} } else {
SpiMode::Mode1 => { let ctrl1_reg = reg_block.slave();
reg_block
.user()
.modify(|_, w| w.tsck_i_edge().set_bit().rsck_i_edge().set_bit());
#[cfg(esp32s2)]
reg_block.ctrl1().modify(|_, w| w.clk_mode_13().set_bit());
#[cfg(not(esp32s2))]
reg_block.slave().modify(|_, w| w.clk_mode_13().set_bit());
}
SpiMode::Mode2 => {
reg_block
.user()
.modify(|_, w| w.tsck_i_edge().set_bit().rsck_i_edge().set_bit());
#[cfg(esp32s2)]
reg_block.ctrl1().modify(|_, w| w.clk_mode_13().clear_bit());
#[cfg(not(esp32s2))]
reg_block.slave().modify(|_, w| w.clk_mode_13().clear_bit());
}
SpiMode::Mode3 => {
reg_block
.user()
.modify(|_, w| w.tsck_i_edge().clear_bit().rsck_i_edge().clear_bit());
#[cfg(esp32s2)]
reg_block.ctrl1().modify(|_, w| w.clk_mode_13().set_bit());
#[cfg(not(esp32s2))]
reg_block.slave().modify(|_, w| w.clk_mode_13().set_bit());
} }
} }
ctrl1_reg.modify(|_, w| {
w.clk_mode_13()
.bit(matches!(data_mode, SpiMode::Mode1 | SpiMode::Mode3))
});
self self
} }