From df7690540893dc11396008cd9d6e640a3289ec21 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?D=C3=A1niel=20Buga?= <bugadani@gmail.com>
Date: Fri, 26 May 2023 19:30:37 +0200
Subject: [PATCH] Fix C3 ADC2 channel assignment

---
 CHANGELOG.md                           | 1 +
 esp-hal-common/src/analog/adc/riscv.rs | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 05ea4dcf3..aee0e1ae5 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -38,6 +38,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - ESP32-S3: Move PSRAM related function to RAM (#546)
 - ADC driver will now apply attenuation values to the correct ADC's channels. (#554)
 - Sometimes half-duplex non-DMA SPI reads were reading garbage in non-release mode (#552)
+- ESP32-C3: Fix GPIO5 ADC channel id (#562)
 
 ### Changed
 
diff --git a/esp-hal-common/src/analog/adc/riscv.rs b/esp-hal-common/src/analog/adc/riscv.rs
index 5639e4296..a2cf87dca 100644
--- a/esp-hal-common/src/analog/adc/riscv.rs
+++ b/esp-hal-common/src/analog/adc/riscv.rs
@@ -337,7 +337,7 @@ pub mod implementation {
 
     impl_adc_interface! {
         ADC2 [
-            (Gpio5, 4),
+            (Gpio5, 0),
         ]
     }
 }