dma: add Mem2Mem to support memory to memory transfer (#1738)
* dma: add Mem2Mem to support memory to memory transfer * fmt * update CHANGELOG * removed some debugging * use "gdma" as the selector for support * fix empty else * clippy * Mem2Mem::new now accepts the peripheral to use * mark Mem2Mem::new() unsafe * fmt :-/ * add Mem2MemN values for gdma on non-esp32s3 tested on esp32c3,esp32c6 (will have an esp32h2 in a few days) * support the esp32c2 (esp8684) * DmaEligible trait providing dma peripheral value & safe constructor for Mem2Mem dma. * added hil-test for Mem2Mem * fmt dma_mem2mem test * remove `debug!()` * reset the mem2mem bit (mem_trans_en) in in_conf0 on drop
This commit is contained in:
liebman
GitHub
parent
4f9dc960c6
commit
cc7077624c
@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- ESP32-S3: Expose optional HSYNC input in LCD_CAM (#1707)
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- ESP32-C6: Support lp-core as wake-up source (#1723)
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- Add support for GPIO wake-up source (#1724)
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- dma: add Mem2Mem to support memory to memory transfer (#1738)
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- Add `uart` wake source (#1727)
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### Fixed
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@ -88,6 +88,13 @@ impl<const N: u8> RegisterAccess for Channel<N> {
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// nothing special to be done here
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}
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#[cfg(gdma)]
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fn set_mem2mem_mode(value: bool) {
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Self::ch()
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.in_conf0()
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.modify(|_, w| w.mem_trans_en().bit(value));
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}
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fn set_out_burstmode(burst_mode: bool) {
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Self::ch().out_conf0().modify(|_, w| {
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w.out_data_burst_en()
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@ -606,3 +613,151 @@ impl<'d> Dma<'d> {
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}
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}
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}
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pub use m2m::*;
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mod m2m {
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use embedded_dma::{ReadBuffer, WriteBuffer};
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use crate::dma::{
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dma_private::{DmaSupport, DmaSupportRx},
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Channel,
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ChannelTypes,
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DescriptorChain,
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DmaDescriptor,
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DmaEligible,
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DmaError,
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DmaPeripheral,
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DmaTransferRx,
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RxPrivate,
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TxPrivate,
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};
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/// DMA Memory to Memory pseudo-Peripheral
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///
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/// This is a pseudo-peripheral that allows for memory to memory transfers.
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/// It is not a real peripheral, but a way to use the DMA engine for memory
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/// to memory transfers.
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pub struct Mem2Mem<'d, C, MODE>
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where
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C: ChannelTypes,
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MODE: crate::Mode,
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{
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channel: Channel<'d, C, MODE>,
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tx_chain: DescriptorChain,
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rx_chain: DescriptorChain,
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peripheral: DmaPeripheral,
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}
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impl<'d, C, MODE> Mem2Mem<'d, C, MODE>
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where
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C: ChannelTypes,
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MODE: crate::Mode,
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{
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/// Create a new Mem2Mem instance.
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pub fn new(
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mut channel: Channel<'d, C, MODE>,
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peripheral: impl DmaEligible,
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tx_descriptors: &'static mut [DmaDescriptor],
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rx_descriptors: &'static mut [DmaDescriptor],
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) -> Self {
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channel.tx.init_channel();
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channel.rx.init_channel();
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Mem2Mem {
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channel,
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peripheral: peripheral.dma_peripheral(),
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tx_chain: DescriptorChain::new(tx_descriptors),
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rx_chain: DescriptorChain::new(rx_descriptors),
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}
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}
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/// Create a new Mem2Mem instance.
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///
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/// # Safety
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///
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/// You must insure that your not using DMA for the same peripheral and
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/// that your the only one using the DmaPeripheral.
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pub unsafe fn new_unsafe(
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mut channel: Channel<'d, C, MODE>,
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peripheral: DmaPeripheral,
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tx_descriptors: &'static mut [DmaDescriptor],
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rx_descriptors: &'static mut [DmaDescriptor],
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) -> Self {
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channel.tx.init_channel();
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channel.rx.init_channel();
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Mem2Mem {
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channel,
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peripheral,
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tx_chain: DescriptorChain::new(tx_descriptors),
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rx_chain: DescriptorChain::new(rx_descriptors),
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}
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}
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/// Start a memory to memory transfer.
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pub fn start_transfer<'t, TXBUF, RXBUF>(
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&mut self,
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tx_buffer: &'t TXBUF,
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rx_buffer: &'t mut RXBUF,
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) -> Result<DmaTransferRx<Self>, DmaError>
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where
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TXBUF: ReadBuffer<Word = u8>,
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RXBUF: WriteBuffer<Word = u8>,
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{
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let (tx_ptr, tx_len) = unsafe { tx_buffer.read_buffer() };
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let (rx_ptr, rx_len) = unsafe { rx_buffer.write_buffer() };
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self.tx_chain.fill_for_tx(false, tx_ptr, tx_len)?;
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self.rx_chain.fill_for_rx(false, rx_ptr, rx_len)?;
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unsafe {
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self.channel
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.tx
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.prepare_transfer_without_start(self.peripheral, &self.tx_chain)?;
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self.channel
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.rx
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.prepare_transfer_without_start(self.peripheral, &self.rx_chain)?;
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self.channel.rx.set_mem2mem_mode(true);
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}
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self.channel.tx.start_transfer()?;
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self.channel.rx.start_transfer()?;
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Ok(DmaTransferRx::new(self))
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}
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}
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impl<'d, C, MODE> Drop for Mem2Mem<'d, C, MODE>
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where
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C: ChannelTypes,
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MODE: crate::Mode,
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{
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fn drop(&mut self) {
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self.channel.rx.set_mem2mem_mode(false);
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}
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}
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impl<'d, C, MODE> DmaSupport for Mem2Mem<'d, C, MODE>
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where
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C: ChannelTypes,
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MODE: crate::Mode,
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{
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fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
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while !self.channel.rx.is_done() {}
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}
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fn peripheral_dma_stop(&mut self) {
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unreachable!("unsupported")
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}
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}
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impl<'d, C, MODE> DmaSupportRx for Mem2Mem<'d, C, MODE>
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where
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C: ChannelTypes,
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MODE: crate::Mode,
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{
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type RX = C::Rx<'d>;
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fn rx(&mut self) -> &mut Self::RX {
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&mut self.channel.rx
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}
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fn chain(&mut self) -> &mut DescriptorChain {
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&mut self.tx_chain
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}
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}
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}
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@ -49,7 +49,7 @@
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//! For convenience you can use the [crate::dma_buffers] macro.
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#![warn(missing_docs)]
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use core::{marker::PhantomData, ptr::addr_of_mut, sync::atomic::compiler_fence};
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use core::{fmt::Debug, marker::PhantomData, ptr::addr_of_mut, sync::atomic::compiler_fence};
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bitfield::bitfield! {
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#[doc(hidden)]
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@ -63,8 +63,19 @@ bitfield::bitfield! {
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owner, set_owner: 31;
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}
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impl Debug for DmaDescriptorFlags {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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f.debug_struct("DmaDescriptorFlags")
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.field("size", &self.size())
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.field("length", &self.length())
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.field("suc_eof", &self.suc_eof())
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.field("owner", &self.owner())
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.finish()
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}
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}
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/// A DMA transfer descriptor.
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#[derive(Clone, Copy)]
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#[derive(Clone, Copy, Debug)]
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pub struct DmaDescriptor {
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pub(crate) flags: DmaDescriptorFlags,
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pub(crate) buffer: *mut u8,
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@ -370,27 +381,45 @@ pub enum DmaPriority {
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[doc(hidden)]
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pub enum DmaPeripheral {
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Spi2 = 0,
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Spi2 = 0,
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#[cfg(any(pdma, esp32s3))]
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Spi3 = 1,
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Spi3 = 1,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem1 = 1,
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#[cfg(any(esp32c3, esp32c6, esp32h2, esp32s3))]
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Uhci0 = 2,
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Uhci0 = 2,
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#[cfg(any(esp32, esp32s2, esp32c3, esp32c6, esp32h2, esp32s3))]
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I2s0 = 3,
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I2s0 = 3,
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#[cfg(any(esp32, esp32s3))]
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I2s1 = 4,
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I2s1 = 4,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem4 = 4,
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#[cfg(esp32s3)]
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LcdCam = 5,
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LcdCam = 5,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem5 = 5,
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#[cfg(not(esp32c2))]
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Aes = 6,
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Aes = 6,
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#[cfg(gdma)]
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Sha = 7,
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Sha = 7,
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#[cfg(any(esp32c3, esp32c6, esp32h2, esp32s3))]
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Adc = 8,
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Adc = 8,
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#[cfg(esp32s3)]
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Rmt = 9,
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Rmt = 9,
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#[cfg(parl_io)]
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ParlIo = 9,
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ParlIo = 9,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem10 = 10,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem11 = 11,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem12 = 12,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem13 = 13,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem14 = 14,
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#[cfg(any(esp32c6, esp32h2))]
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Mem2Mem15 = 15,
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}
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#[derive(PartialEq, PartialOrd)]
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@ -408,6 +437,16 @@ impl From<u32> for Owner {
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}
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}
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/// Marks channels as useable for SPI
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#[doc(hidden)]
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pub trait DmaEligible {
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/// The DMA peripheral
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const DMA_PERIPHERAL: DmaPeripheral;
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fn dma_peripheral(&self) -> DmaPeripheral {
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Self::DMA_PERIPHERAL
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}
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}
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/// Marks channels as useable for SPI
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#[doc(hidden)]
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pub trait SpiPeripheral: PeripheralMarker {}
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@ -458,6 +497,7 @@ pub trait Tx: TxPrivate {}
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pub trait PeripheralMarker {}
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#[doc(hidden)]
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#[derive(Debug)]
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pub struct DescriptorChain {
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pub(crate) descriptors: &'static mut [DmaDescriptor],
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}
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@ -877,6 +917,9 @@ pub trait RxPrivate: crate::private::Sealed {
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fn start_transfer(&mut self) -> Result<(), DmaError>;
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#[cfg(gdma)]
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fn set_mem2mem_mode(&mut self, value: bool);
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fn listen_ch_in_done(&self);
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fn clear_ch_in_done(&self);
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@ -1042,6 +1085,11 @@ where
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self.rx_impl.start_transfer()
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}
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#[cfg(gdma)]
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fn set_mem2mem_mode(&mut self, value: bool) {
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R::set_mem2mem_mode(value);
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}
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fn listen_ch_in_done(&self) {
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R::listen_ch_in_done();
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}
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@ -1411,6 +1459,8 @@ where
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#[doc(hidden)]
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pub trait RegisterAccess: crate::private::Sealed {
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fn init_channel();
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#[cfg(gdma)]
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fn set_mem2mem_mode(value: bool);
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fn set_out_burstmode(burst_mode: bool);
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fn set_out_priority(priority: DmaPriority);
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fn clear_out_interrupts();
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@ -204,6 +204,16 @@ where
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impl<T> crate::private::Sealed for &mut T where T: crate::private::Sealed {}
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mod peripheral_macros {
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#[doc(hidden)]
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#[macro_export]
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macro_rules! impl_dma_eligible {
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($name:ident,$dma:ident) => {
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impl $crate::dma::DmaEligible for $name {
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const DMA_PERIPHERAL: $crate::dma::DmaPeripheral = $crate::dma::DmaPeripheral::$dma;
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}
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};
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! peripherals {
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@ -215,6 +225,49 @@ mod peripheral_macros {
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$(
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$crate::create_peripheral!($(#[$cfg])? $name <= $from_pac);
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)*
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$crate::impl_dma_eligible!(SPI2,Spi2);
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#[cfg(any(pdma, esp32s3))]
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$crate::impl_dma_eligible!(SPI3,Spi3);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM1,Mem2Mem1);
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#[cfg(any(esp32c3, esp32c6, esp32h2, esp32s3))]
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$crate::impl_dma_eligible!(UHCI0,Uhci0);
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#[cfg(any(esp32, esp32s2, esp32c3, esp32c6, esp32h2, esp32s3))]
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$crate::impl_dma_eligible!(I2S0,I2s0);
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#[cfg(any(esp32, esp32s3))]
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$crate::impl_dma_eligible!(I2S1,I2s1);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM4,Mem2Mem4);
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#[cfg(esp32s3)]
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$crate::impl_dma_eligible!(LCD_CAM,LcdCam);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM5,Mem2Mem5);
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#[cfg(not(esp32c2))]
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$crate::impl_dma_eligible!(AES,Aes);
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#[cfg(gdma)]
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$crate::impl_dma_eligible!(SHA,Sha);
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#[cfg(any(esp32c3, esp32c6, esp32h2, esp32s3))]
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$crate::impl_dma_eligible!(ADC1,Adc);
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#[cfg(any(esp32c3, esp32s3))]
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$crate::impl_dma_eligible!(ADC2,Adc);
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#[cfg(esp32s3)]
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$crate::impl_dma_eligible!(RMT,Rmt);
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#[cfg(parl_io)]
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$crate::impl_dma_eligible!(PARL_IO,ParlIo);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM10,Mem2Mem10);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM11,Mem2Mem11);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM12,Mem2Mem12);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM13,Mem2Mem13);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM14,Mem2Mem14);
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#[cfg(any(esp32c6, esp32h2))]
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$crate::impl_dma_eligible!(MEM2MEM15,Mem2Mem15);
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}
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#[allow(non_snake_case)]
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@ -48,4 +48,11 @@ crate::peripherals! {
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UART1 <= UART1,
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WIFI <= virtual,
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XTS_AES <= XTS_AES,
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MEM2MEM1 <= virtual,
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MEM2MEM2 <= virtual,
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MEM2MEM3 <= virtual,
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MEM2MEM4 <= virtual,
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MEM2MEM5 <= virtual,
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MEM2MEM6 <= virtual,
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MEM2MEM8 <= virtual,
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}
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@ -87,4 +87,13 @@ crate::peripherals! {
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UHCI0 <= UHCI0,
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USB_DEVICE <= USB_DEVICE,
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WIFI <= virtual,
|
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MEM2MEM1 <= virtual,
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MEM2MEM4 <= virtual,
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MEM2MEM5 <= virtual,
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MEM2MEM10 <= virtual,
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MEM2MEM11 <= virtual,
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MEM2MEM12 <= virtual,
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MEM2MEM13 <= virtual,
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MEM2MEM14 <= virtual,
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MEM2MEM15 <= virtual,
|
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}
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||||
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@ -77,4 +77,13 @@ crate::peripherals! {
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UART1 <= UART1,
|
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UHCI0 <= UHCI0,
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USB_DEVICE <= USB_DEVICE,
|
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MEM2MEM1 <= virtual,
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MEM2MEM4 <= virtual,
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MEM2MEM5 <= virtual,
|
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MEM2MEM10 <= virtual,
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MEM2MEM11 <= virtual,
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MEM2MEM12 <= virtual,
|
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MEM2MEM13 <= virtual,
|
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MEM2MEM14 <= virtual,
|
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MEM2MEM15 <= virtual,
|
||||
}
|
||||
|
||||
78
examples/src/bin/dma_mem2mem.rs
Normal file
78
examples/src/bin/dma_mem2mem.rs
Normal file
@ -0,0 +1,78 @@
|
||||
//! Uses DMA to copy memory to memory.
|
||||
|
||||
//% FEATURES: esp-hal/log
|
||||
//% CHIPS: esp32s3 esp32c2 esp32c3 esp32c6 esp32h2
|
||||
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use esp_backtrace as _;
|
||||
use esp_hal::{
|
||||
clock::ClockControl,
|
||||
delay::Delay,
|
||||
dma::{Dma, DmaPriority, Mem2Mem},
|
||||
dma_buffers,
|
||||
peripherals::Peripherals,
|
||||
prelude::*,
|
||||
system::SystemControl,
|
||||
};
|
||||
use log::{error, info};
|
||||
|
||||
const DATA_SIZE: usize = 1024 * 10;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
esp_println::logger::init_logger(log::LevelFilter::Info);
|
||||
|
||||
let peripherals = Peripherals::take();
|
||||
let system = SystemControl::new(peripherals.SYSTEM);
|
||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||
let delay = Delay::new(&clocks);
|
||||
|
||||
let (tx_buffer, tx_descriptors, mut rx_buffer, rx_descriptors) = dma_buffers!(DATA_SIZE);
|
||||
|
||||
let dma = Dma::new(peripherals.DMA);
|
||||
let channel = dma.channel0.configure(false, DmaPriority::Priority0);
|
||||
#[cfg(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3"))]
|
||||
let dma_peripheral = peripherals.SPI2;
|
||||
#[cfg(not(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3")))]
|
||||
let dma_peripheral = peripherals.MEM2MEM1;
|
||||
|
||||
let mut mem2mem = Mem2Mem::new(channel, dma_peripheral, tx_descriptors, rx_descriptors);
|
||||
|
||||
for i in 0..core::mem::size_of_val(tx_buffer) {
|
||||
tx_buffer[i] = (i % 256) as u8;
|
||||
}
|
||||
|
||||
info!("Starting transfer of {} bytes", DATA_SIZE);
|
||||
let result = mem2mem.start_transfer(&tx_buffer, &mut rx_buffer);
|
||||
match result {
|
||||
Ok(dma_wait) => {
|
||||
info!("Transfer started");
|
||||
dma_wait.wait().unwrap();
|
||||
info!("Transfer completed, comparing buffer");
|
||||
let mut error = false;
|
||||
for i in 0..core::mem::size_of_val(tx_buffer) {
|
||||
if rx_buffer[i] != tx_buffer[i] {
|
||||
error!(
|
||||
"Error: tx_buffer[{}] = {}, rx_buffer[{}] = {}",
|
||||
i, tx_buffer[i], i, rx_buffer[i]
|
||||
);
|
||||
error = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if !error {
|
||||
info!("Buffers are equal");
|
||||
}
|
||||
info!("Done");
|
||||
}
|
||||
Err(e) => {
|
||||
error!("start_transfer: Error: {:?}", e);
|
||||
}
|
||||
}
|
||||
|
||||
loop {
|
||||
delay.delay(2.secs());
|
||||
}
|
||||
}
|
||||
@ -24,6 +24,10 @@ harness = false
|
||||
name = "delay"
|
||||
harness = false
|
||||
|
||||
[[test]]
|
||||
name = "dma_mem2mem"
|
||||
harness = false
|
||||
|
||||
[[test]]
|
||||
name = "ecc"
|
||||
harness = false
|
||||
|
||||
59
hil-test/tests/dma_mem2mem.rs
Normal file
59
hil-test/tests/dma_mem2mem.rs
Normal file
@ -0,0 +1,59 @@
|
||||
//! DMA Mem2Mem Tests
|
||||
|
||||
//% CHIPS: esp32s3 esp32c2 esp32c3 esp32c6 esp32h2
|
||||
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use defmt_rtt as _;
|
||||
use esp_backtrace as _;
|
||||
use esp_hal::{
|
||||
clock::ClockControl,
|
||||
dma::{Dma, DmaPriority, Mem2Mem},
|
||||
dma_buffers,
|
||||
peripherals::Peripherals,
|
||||
system::SystemControl,
|
||||
};
|
||||
|
||||
const DATA_SIZE: usize = 1024 * 10;
|
||||
|
||||
#[cfg(test)]
|
||||
#[embedded_test::tests]
|
||||
mod tests {
|
||||
use defmt::assert_eq;
|
||||
|
||||
use super::*;
|
||||
|
||||
#[init]
|
||||
fn init() {}
|
||||
|
||||
#[test]
|
||||
fn test_internal_mem2mem() {
|
||||
let peripherals = Peripherals::take();
|
||||
let system = SystemControl::new(peripherals.SYSTEM);
|
||||
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||
|
||||
let (tx_buffer, tx_descriptors, mut rx_buffer, rx_descriptors) = dma_buffers!(DATA_SIZE);
|
||||
|
||||
let dma = Dma::new(peripherals.DMA);
|
||||
let channel = dma.channel0.configure(false, DmaPriority::Priority0);
|
||||
#[cfg(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3"))]
|
||||
let dma_peripheral = peripherals.SPI2;
|
||||
#[cfg(not(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3")))]
|
||||
let dma_peripheral = peripherals.MEM2MEM1;
|
||||
|
||||
let mut mem2mem = Mem2Mem::new(channel, dma_peripheral, tx_descriptors, rx_descriptors);
|
||||
|
||||
for i in 0..core::mem::size_of_val(tx_buffer) {
|
||||
tx_buffer[i] = (i % 256) as u8;
|
||||
}
|
||||
let dma_wait = mem2mem.start_transfer(&tx_buffer, &mut rx_buffer).unwrap();
|
||||
dma_wait.wait().unwrap();
|
||||
// explicitly drop to insure the mem2mem bit is not left set as this causes
|
||||
// subsequent dma tests to fail.
|
||||
drop(mem2mem);
|
||||
for i in 0..core::mem::size_of_val(tx_buffer) {
|
||||
assert_eq!(rx_buffer[i], tx_buffer[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user