Fix naming violations for spi::Mode enum variants (#2902)
* Fix naming violations for `spi::Mode` * Update migration guide * Update `CHANGELOG.md`
This commit is contained in:
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@ -95,6 +95,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- UART: Fix naming violations for `DataBits`, `Parity`, and `StopBits` enum variants (#2893)
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- UART: Fix naming violations for `DataBits`, `Parity`, and `StopBits` enum variants (#2893)
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- UART: Remove blocking version of `read_bytes` and rename `drain_fifo` to `read_bytes` instead (#2895)
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- UART: Remove blocking version of `read_bytes` and rename `drain_fifo` to `read_bytes` instead (#2895)
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- Renamed variants of `CpuClock`, made the enum non-exhaustive (#2899)
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- Renamed variants of `CpuClock`, made the enum non-exhaustive (#2899)
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- SPI: Fix naming violations for `Mode` enum variants (#2902)
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### Fixed
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### Fixed
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@ -245,7 +245,7 @@ is not compatible with the hardware.
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peripherals.SPI2,
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peripherals.SPI2,
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Config {
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Config {
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frequency: 100.kHz(),
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frequency: 100.kHz(),
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mode: SpiMode::Mode0,
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mode: SpiMode::_0,
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..Config::default()
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..Config::default()
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},
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},
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-);
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-);
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@ -405,3 +405,12 @@ The specific CPU clock variants are renamed from e.g. `Clock80MHz` to `_80MHz`.
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```
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```
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Additionally the enum is marked as non-exhaustive.
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Additionally the enum is marked as non-exhaustive.
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## SPI Modes
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The SPI mode variants are renamed from e.g. `Mode0` to `_0`.
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```diff
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- Mode::Mode0
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+ Mode::_0
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```
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@ -28,7 +28,7 @@
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//!
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//!
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//! let mut spi = Spi::new(
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//! let mut spi = Spi::new(
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//! peripherals.SPI2,
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//! peripherals.SPI2,
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//! Config::default().with_frequency(100.kHz()).with_mode(Mode::Mode0)
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//! Config::default().with_frequency(100.kHz()).with_mode(Mode::_0)
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//! )
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//! )
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//! .unwrap()
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//! .unwrap()
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//! .with_sck(sclk)
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//! .with_sck(sclk)
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@ -44,7 +44,7 @@
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//!
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//!
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//! let mut spi = Spi::new(
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//! let mut spi = Spi::new(
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//! peripherals.SPI2,
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//! peripherals.SPI2,
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//! Config::default().with_frequency(100.kHz()).with_mode(Mode::Mode0)
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//! Config::default().with_frequency(100.kHz()).with_mode(Mode::_0)
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//! )
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//! )
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//! .unwrap()
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//! .unwrap()
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//! .with_sck(sclk)
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//! .with_sck(sclk)
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@ -469,7 +469,7 @@ impl Default for Config {
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use fugit::RateExtU32;
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use fugit::RateExtU32;
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Config {
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Config {
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frequency: 1_u32.MHz(),
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frequency: 1_u32.MHz(),
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mode: Mode::Mode0,
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mode: Mode::_0,
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read_bit_order: BitOrder::MsbFirst,
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read_bit_order: BitOrder::MsbFirst,
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write_bit_order: BitOrder::MsbFirst,
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write_bit_order: BitOrder::MsbFirst,
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}
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}
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@ -2945,11 +2945,11 @@ impl Driver {
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pin_reg.modify(|_, w| {
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pin_reg.modify(|_, w| {
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w.ck_idle_edge()
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w.ck_idle_edge()
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.bit(matches!(data_mode, Mode::Mode2 | Mode::Mode3))
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.bit(matches!(data_mode, Mode::_2 | Mode::_3))
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});
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});
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reg_block.user().modify(|_, w| {
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reg_block.user().modify(|_, w| {
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w.ck_out_edge()
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w.ck_out_edge()
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.bit(matches!(data_mode, Mode::Mode1 | Mode::Mode2))
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.bit(matches!(data_mode, Mode::_1 | Mode::_2))
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});
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});
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}
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}
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@ -71,16 +71,16 @@ impl embedded_hal::spi::Error for Error {
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pub enum Mode {
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pub enum Mode {
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/// Mode 0 (CPOL = 0, CPHA = 0): Clock is low when idle, data is captured on
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/// Mode 0 (CPOL = 0, CPHA = 0): Clock is low when idle, data is captured on
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/// the rising edge and propagated on the falling edge.
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/// the rising edge and propagated on the falling edge.
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Mode0,
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_0,
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/// Mode 1 (CPOL = 0, CPHA = 1): Clock is low when idle, data is captured on
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/// Mode 1 (CPOL = 0, CPHA = 1): Clock is low when idle, data is captured on
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/// the falling edge and propagated on the rising edge.
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/// the falling edge and propagated on the rising edge.
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Mode1,
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_1,
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/// Mode 2 (CPOL = 1, CPHA = 0): Clock is high when idle, data is captured
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/// Mode 2 (CPOL = 1, CPHA = 0): Clock is high when idle, data is captured
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/// on the falling edge and propagated on the rising edge.
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/// on the falling edge and propagated on the rising edge.
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Mode2,
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_2,
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/// Mode 3 (CPOL = 1, CPHA = 1): Clock is high when idle, data is captured
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/// Mode 3 (CPOL = 1, CPHA = 1): Clock is high when idle, data is captured
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/// on the rising edge and propagated on the falling edge.
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/// on the rising edge and propagated on the falling edge.
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Mode3,
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_3,
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}
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}
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/// SPI Bit Order
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/// SPI Bit Order
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@ -29,7 +29,7 @@
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//! dma_buffers!(32000);
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//! dma_buffers!(32000);
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//! let mut spi = Spi::new(
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//! let mut spi = Spi::new(
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//! peripherals.SPI2,
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//! peripherals.SPI2,
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//! Mode::Mode0,
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//! Mode::_0,
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//! )
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//! )
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//! .with_sck(sclk)
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//! .with_sck(sclk)
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//! .with_mosi(mosi)
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//! .with_mosi(mosi)
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@ -699,33 +699,32 @@ impl Info {
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{
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{
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reg_block.pin().modify(|_, w| {
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reg_block.pin().modify(|_, w| {
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w.ck_idle_edge()
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w.ck_idle_edge()
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.bit(matches!(data_mode, Mode::Mode0 | Mode::Mode1))
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.bit(matches!(data_mode, Mode::_0 | Mode::_1))
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});
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reg_block.user().modify(|_, w| {
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w.ck_i_edge()
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.bit(matches!(data_mode, Mode::Mode1 | Mode::Mode2))
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});
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});
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reg_block
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.user()
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.modify(|_, w| w.ck_i_edge().bit(matches!(data_mode, Mode::_1 | Mode::_2)));
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reg_block.ctrl2().modify(|_, w| unsafe {
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reg_block.ctrl2().modify(|_, w| unsafe {
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match data_mode {
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match data_mode {
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Mode::Mode0 => {
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Mode::_0 => {
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w.miso_delay_mode().bits(0);
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w.miso_delay_mode().bits(0);
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w.miso_delay_num().bits(0);
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w.miso_delay_num().bits(0);
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w.mosi_delay_mode().bits(2);
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w.mosi_delay_mode().bits(2);
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w.mosi_delay_num().bits(2)
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w.mosi_delay_num().bits(2)
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}
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}
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Mode::Mode1 => {
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Mode::_1 => {
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w.miso_delay_mode().bits(2);
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w.miso_delay_mode().bits(2);
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w.miso_delay_num().bits(0);
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w.miso_delay_num().bits(0);
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w.mosi_delay_mode().bits(0);
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w.mosi_delay_mode().bits(0);
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w.mosi_delay_num().bits(0)
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w.mosi_delay_num().bits(0)
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}
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}
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Mode::Mode2 => {
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Mode::_2 => {
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w.miso_delay_mode().bits(0);
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w.miso_delay_mode().bits(0);
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w.miso_delay_num().bits(0);
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w.miso_delay_num().bits(0);
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w.mosi_delay_mode().bits(1);
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w.mosi_delay_mode().bits(1);
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w.mosi_delay_num().bits(2)
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w.mosi_delay_num().bits(2)
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}
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}
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Mode::Mode3 => {
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Mode::_3 => {
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w.miso_delay_mode().bits(1);
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w.miso_delay_mode().bits(1);
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w.miso_delay_num().bits(0);
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w.miso_delay_num().bits(0);
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w.mosi_delay_mode().bits(0);
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w.mosi_delay_mode().bits(0);
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@ -736,7 +735,7 @@ impl Info {
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if dma {
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if dma {
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assert!(
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assert!(
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matches!(data_mode, Mode::Mode1 | Mode::Mode3),
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matches!(data_mode, Mode::_1 | Mode::_3),
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"Mode {:?} is not supported with DMA",
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"Mode {:?} is not supported with DMA",
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data_mode
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data_mode
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);
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);
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@ -755,13 +754,13 @@ impl Info {
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}
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}
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reg_block.user().modify(|_, w| {
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reg_block.user().modify(|_, w| {
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w.tsck_i_edge()
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w.tsck_i_edge()
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.bit(matches!(data_mode, Mode::Mode1 | Mode::Mode2));
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.bit(matches!(data_mode, Mode::_1 | Mode::_2));
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w.rsck_i_edge()
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w.rsck_i_edge()
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.bit(matches!(data_mode, Mode::Mode1 | Mode::Mode2))
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.bit(matches!(data_mode, Mode::_1 | Mode::_2))
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});
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});
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ctrl1_reg.modify(|_, w| {
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ctrl1_reg.modify(|_, w| {
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w.clk_mode_13()
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w.clk_mode_13()
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.bit(matches!(data_mode, Mode::Mode1 | Mode::Mode3))
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.bit(matches!(data_mode, Mode::_1 | Mode::_3))
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});
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});
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}
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}
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}
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}
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@ -61,7 +61,7 @@ async fn main(_spawner: Spawner) {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -43,7 +43,7 @@ fn main() -> ! {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -93,7 +93,7 @@ fn main() -> ! {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -64,7 +64,7 @@ fn main() -> ! {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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let mut spi = Spi::new(peripherals.SPI2, Mode::Mode0)
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let mut spi = Spi::new(peripherals.SPI2, Mode::_0)
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.with_sck(slave_sclk)
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.with_sck(slave_sclk)
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.with_mosi(slave_mosi)
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.with_mosi(slave_mosi)
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.with_miso(slave_miso)
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.with_miso(slave_miso)
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@ -121,7 +121,7 @@ mod test {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(10000.kHz())
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.with_frequency(10000.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_miso(unsafe { mosi.clone_unchecked() })
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.with_miso(unsafe { mosi.clone_unchecked() })
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@ -135,7 +135,7 @@ mod test {
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peripherals.SPI3,
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peripherals.SPI3,
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Config::default()
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Config::default()
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.with_frequency(10000.kHz())
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.with_frequency(10000.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_dma(dma_channel2)
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.with_dma(dma_channel2)
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@ -229,7 +229,7 @@ mod test {
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peripherals.spi,
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peripherals.spi,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_dma(peripherals.dma_channel)
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.with_dma(peripherals.dma_channel)
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@ -212,7 +212,7 @@ mod tests {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap();
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.unwrap();
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@ -50,7 +50,7 @@ mod tests {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -54,7 +54,7 @@ mod tests {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -66,7 +66,7 @@ mod tests {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -125,7 +125,7 @@ mod tests {
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let miso = unsafe { miso_gpio.clone_unchecked() }.into_peripheral_output();
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let miso = unsafe { miso_gpio.clone_unchecked() }.into_peripheral_output();
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Context {
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Context {
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spi: Spi::new(peripherals.SPI2, Mode::Mode1)
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spi: Spi::new(peripherals.SPI2, Mode::_1)
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.with_sck(sclk)
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.with_sck(sclk)
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.with_mosi(mosi)
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.with_mosi(mosi)
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.with_miso(miso)
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.with_miso(miso)
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@ -81,7 +81,7 @@ fn main() -> ! {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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@ -67,7 +67,7 @@ fn main() -> ! {
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peripherals.SPI2,
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peripherals.SPI2,
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Config::default()
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Config::default()
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.with_frequency(100.kHz())
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.with_frequency(100.kHz())
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.with_mode(Mode::Mode0),
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.with_mode(Mode::_0),
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)
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)
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.unwrap()
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.unwrap()
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.with_sck(sclk)
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.with_sck(sclk)
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