Gpio cleanup (#2157)

* InterruptStatusRegisterAccess

* GpioRegisterAccess

* Remove GpioProperties

* Hide private methods

* Simplify the analog macro

* Fix typo

* Remove unused NMI status read

* Hide ISRA

* Fix macro syntax

* Simplify rtc_pins macro

* Fix type name

esp-hal/src/gpio/etm.rs

@@ -154,7 +154,7 @@ impl<const C: u8> GpioEtmEventChannel<C> {
 
         pin.init_input(pin_config.pull, private::Internal);
 
-        enable_event_channel(C, pin.number(private::Internal));
+        enable_event_channel(C, pin.number());
         GpioEtmEventChannelRising { _pin: pin }
     }
 
@@ -171,7 +171,7 @@ impl<const C: u8> GpioEtmEventChannel<C> {
 
         pin.init_input(pin_config.pull, private::Internal);
 
-        enable_event_channel(C, pin.number(private::Internal));
+        enable_event_channel(C, pin.number());
         GpioEtmEventChannelFalling { _pin: pin }
     }
 
@@ -188,7 +188,7 @@ impl<const C: u8> GpioEtmEventChannel<C> {
 
         pin.init_input(pin_config.pull, private::Internal);
 
-        enable_event_channel(C, pin.number(private::Internal));
+        enable_event_channel(C, pin.number());
         GpioEtmEventChannelAny { _pin: pin }
     }
 }
@@ -312,7 +312,7 @@ impl<const C: u8> GpioEtmTaskChannel<C> {
             pin.set_to_push_pull_output(private::Internal);
         }
 
-        enable_task_channel(C, pin.number(private::Internal));
+        enable_task_channel(C, pin.number());
         GpioEtmTaskSet { _pin: pin }
     }
 
@@ -335,7 +335,7 @@ impl<const C: u8> GpioEtmTaskChannel<C> {
             pin.set_to_push_pull_output(private::Internal);
         }
 
-        enable_task_channel(C, pin.number(private::Internal));
+        enable_task_channel(C, pin.number());
         GpioEtmTaskClear { _pin: pin }
     }
 
@@ -358,7 +358,7 @@ impl<const C: u8> GpioEtmTaskChannel<C> {
             pin.set_to_push_pull_output(private::Internal);
         }
 
-        enable_task_channel(C, pin.number(private::Internal));
+        enable_task_channel(C, pin.number());
         GpioEtmTaskToggle { _pin: pin }
     }
 }

esp-hal/src/gpio/interconnect.rs

@@ -6,7 +6,6 @@ use crate::{
         AlternateFunction,
         AnyPin,
         GpioPin,
-        GpioProperties,
         InputPin,
         Level,
         NoPin,
@@ -117,8 +116,7 @@ impl PeripheralInput for InputSignal {
         let af = if self.is_inverted {
             GPIO_FUNCTION
         } else {
-            self.pin
+            self.input_signals(private::Internal)
-                .input_signals(private::Internal)
                 .into_iter()
                 .position(|s| s == Some(signal))
                 .ok_or(())
@@ -133,11 +131,7 @@ impl PeripheralInput for InputSignal {
         self.pin.set_alternate_function(af, private::Internal);
 
         if signal_nr <= INPUT_SIGNAL_MAX as usize {
-            self.connect(
+            self.connect(signal_nr, self.is_inverted, self.pin.number());
-                signal_nr,
-                self.is_inverted,
-                self.pin.number(private::Internal),
-            );
         }
     }
 
@@ -159,11 +153,14 @@ impl PeripheralInput for InputSignal {
             .modify(|_, w| w.sel().clear_bit());
     }
 
+    fn input_signals(&self, _: private::Internal) -> [Option<gpio::InputSignal>; 6] {
+        PeripheralInput::input_signals(&self.pin, private::Internal)
+    }
+
     delegate::delegate! {
         to self.pin {
             fn init_input(&self, pull: Pull, _internal: private::Internal);
             fn is_input_high(&self, _internal: private::Internal) -> bool;
-            fn input_signals(&self, _internal: private::Internal) -> [Option<gpio::InputSignal>; 6];
             fn enable_input(&mut self, on: bool, _internal: private::Internal);
             fn enable_input_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
         }
@@ -266,8 +263,7 @@ impl PeripheralOutput for OutputSignal {
         let af = if self.is_inverted {
             GPIO_FUNCTION
         } else {
-            self.pin
+            self.output_signals(private::Internal)
-                .output_signals(private::Internal)
                 .into_iter()
                 .position(|s| s == Some(signal))
                 .ok_or(())
@@ -288,7 +284,7 @@ impl PeripheralOutput for OutputSignal {
             self.is_inverted,
             false,
             false,
-            self.pin.number(private::Internal),
+            self.pin.number(),
         );
     }
 
@@ -310,6 +306,10 @@ impl PeripheralOutput for OutputSignal {
             .modify(|_, w| w.sel().clear_bit());
     }
 
+    fn output_signals(&self, _: private::Internal) -> [Option<gpio::OutputSignal>; 6] {
+        PeripheralOutput::output_signals(&self.pin, private::Internal)
+    }
+
     delegate::delegate! {
         to self.pin {
             fn set_to_open_drain_output(&mut self, _internal: private::Internal);
@@ -322,7 +322,6 @@ impl PeripheralOutput for OutputSignal {
             fn internal_pull_up_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
             fn internal_pull_down_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
             fn is_set_high(&self, _internal: private::Internal) -> bool;
-            fn output_signals(&self, _internal: private::Internal) -> [Option<gpio::OutputSignal>; 6];
         }
     }
 }
@@ -372,7 +371,7 @@ impl From<AnyPin> for AnyInputSignal {
 
 impl<const GPIONUM: u8> From<GpioPin<GPIONUM>> for AnyInputSignal
 where
-    GpioPin<GPIONUM>: InputPin + GpioProperties,
+    GpioPin<GPIONUM>: InputPin,
 {
     fn from(pin: GpioPin<GPIONUM>) -> Self {
         Self(AnyInputSignalInner::Input(pin.peripheral_input()))

esp-hal/src/rtc_cntl/sleep/esp32c6.rs

@@ -5,7 +5,6 @@ use crate::{
     efuse::Efuse,
     gpio::{Pins, RtcFunction},
     peripherals::Peripherals,
-    private,
     rtc_cntl::{
         rtc::{
             rtc_clk_cpu_freq_set_xtal,
@@ -77,7 +76,7 @@ impl Ext1WakeupSource<'_, '_> {
         use crate::gpio::RtcPin;
 
         fn uninit_pin(pin: &mut impl RtcPin, wakeup_pins: u8) {
-            if wakeup_pins & (1 << pin.number(private::Internal)) != 0 {
+            if wakeup_pins & (1 << pin.number()) != 0 {
                 pin.rtcio_pad_hold(false);
                 pin.rtc_set_config(false, false, RtcFunction::Rtc);
             }
@@ -110,9 +109,9 @@ impl WakeSource for Ext1WakeupSource<'_, '_> {
         let mut pin_mask = 0u8;
         let mut level_mask = 0u8;
         for (pin, level) in pins.iter_mut() {
-            pin_mask |= 1 << pin.number(private::Internal);
+            pin_mask |= 1 << pin.number();
             level_mask |= match level {
-                WakeupLevel::High => 1 << pin.number(private::Internal),
+                WakeupLevel::High => 1 << pin.number(),
                 WakeupLevel::Low => 0,
             };
 

esp-hal/src/rtc_cntl/sleep/esp32s3.rs

@@ -240,14 +240,12 @@ impl<'a, 'b> RtcioWakeupSource<'a, 'b> {
 
         pin.rtc_set_config(true, true, RtcFunction::Rtc);
 
-        rtcio
+        rtcio.pin(pin.number() as usize).modify(|_, w| unsafe {
-            .pin(pin.number(crate::private::Internal) as usize)
+            w.wakeup_enable().set_bit().int_type().bits(match level {
-            .modify(|_, w| unsafe {
+                WakeupLevel::Low => 4,
-                w.wakeup_enable().set_bit().int_type().bits(match level {
+                WakeupLevel::High => 5,
-                    WakeupLevel::Low => 4,
+            })
-                    WakeupLevel::High => 5,
+        });
-                })
-            });
     }
 }
 

esp-hal/src/soc/esp32/gpio.rs

@@ -36,11 +36,6 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
@@ -48,13 +43,7 @@
 use core::mem::transmute;
 
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-        InterruptStatusRegisterAccessBank1,
-    },
     peripherals::{io_mux, GPIO, IO_MUX},
     Cpu,
 };
@@ -804,45 +793,45 @@ crate::gpio::gpio! {
 }
 
 crate::gpio::analog! {
-    (36, 0,  sensor_pads(),   sense1_mux_sel, sense1_fun_sel, sense1_fun_ie)
+    (36, 0,  sensor_pads(),  "sense1_"    )
-    (37, 1,  sensor_pads(),   sense2_mux_sel, sense2_fun_sel, sense2_fun_ie)
+    (37, 1,  sensor_pads(),  "sense2_"    )
-    (38, 2,  sensor_pads(),   sense3_mux_sel, sense3_fun_sel, sense3_fun_ie)
+    (38, 2,  sensor_pads(),  "sense3_"    )
-    (39, 3,  sensor_pads(),   sense4_mux_sel, sense4_fun_sel, sense4_fun_ie)
+    (39, 3,  sensor_pads(),  "sense4_"    )
-    (34, 4,  adc_pad(),         adc1_mux_sel,   adc1_fun_sel,   adc1_fun_ie)
+    (34, 4,  adc_pad(),      "adc1_"      )
-    (35, 5,  adc_pad(),         adc2_mux_sel,   adc2_fun_sel,   adc1_fun_ie)
+    (35, 5,  adc_pad(),      "adc2_"      )
-    (25, 6,  pad_dac1(),             mux_sel,        fun_sel,        fun_ie, rue,       rde)
+    (25, 6,  pad_dac1(),     "",      true)
-    (26, 7,  pad_dac2(),             mux_sel,        fun_sel,        fun_ie, rue,       rde)
+    (26, 7,  pad_dac2(),     "",      true)
-    (33, 8,  xtal_32k_pad(),    x32n_mux_sel,   x32n_fun_sel,   x32n_fun_ie, x32n_rue,  x32n_rde )
+    (33, 8,  xtal_32k_pad(), "x32p_", true)
-    (32, 9,  xtal_32k_pad(),    x32p_mux_sel,   x32p_fun_sel,   x32p_fun_ie, x32p_rue,  x32p_rde )
+    (32, 9,  xtal_32k_pad(), "x32n_", true)
-    (4,  10, touch_pad0(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (4,  10, touch_pad0(),   "",      true)
-    (0,  11, touch_pad1(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (0,  11, touch_pad1(),   "",      true)
-    (2,  12, touch_pad2(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (2,  12, touch_pad2(),   "",      true)
-    (15, 13, touch_pad3(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (15, 13, touch_pad3(),   "",      true)
-    (13, 14, touch_pad4(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (13, 14, touch_pad4(),   "",      true)
-    (12, 15, touch_pad5(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (12, 15, touch_pad5(),   "",      true)
-    (14, 16, touch_pad6(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (14, 16, touch_pad6(),   "",      true)
-    (27, 17, touch_pad7(),           mux_sel,        fun_sel,        fun_ie, rue,       rde      )
+    (27, 17, touch_pad7(),   "",      true)
 }
 
 crate::gpio::rtc_pins! {
-    (36, 0,  sensor_pads(),    sense1_, sense1_hold_force )
+    (36, 0,  sensor_pads(),    sense1_, sense1_hold_force          )
-    (37, 1,  sensor_pads(),    sense2_, sense2_hold_force )
+    (37, 1,  sensor_pads(),    sense2_, sense2_hold_force          )
-    (38, 2,  sensor_pads(),    sense3_, sense3_hold_force )
+    (38, 2,  sensor_pads(),    sense3_, sense3_hold_force          )
-    (39, 3,  sensor_pads(),    sense4_, sense4_hold_force )
+    (39, 3,  sensor_pads(),    sense4_, sense4_hold_force          )
-    (34, 4,  adc_pad(),        adc1_,   adc1_hold_force )
+    (34, 4,  adc_pad(),        adc1_,   adc1_hold_force            )
-    (35, 5,  adc_pad(),        adc2_,   adc2_hold_force )
+    (35, 5,  adc_pad(),        adc2_,   adc2_hold_force            )
-    (25, 6,  pad_dac1(),       "",      pdac1_hold_force,      rue,       rde )
+    (25, 6,  pad_dac1(),       "",      pdac1_hold_force,      true)
-    (26, 7,  pad_dac2(),       "",      pdac2_hold_force,      rue,       rde )
+    (26, 7,  pad_dac2(),       "",      pdac2_hold_force,      true)
-    (33, 8,  xtal_32k_pad(),   x32n_,   x32n_hold_force,       x32n_rue,  x32n_rde  )
+    (33, 8,  xtal_32k_pad(),   x32n_,   x32n_hold_force,       true)
-    (32, 9,  xtal_32k_pad(),   x32p_,   x32p_hold_force,       x32p_rue,  x32p_rde  )
+    (32, 9,  xtal_32k_pad(),   x32p_,   x32p_hold_force,       true)
-    (4,  10, touch_pad0(),     "",      touch_pad0_hold_force, rue,       rde       )
+    (4,  10, touch_pad0(),     "",      touch_pad0_hold_force, true)
-    (0,  11, touch_pad1(),     "",      touch_pad1_hold_force, rue,       rde       )
+    (0,  11, touch_pad1(),     "",      touch_pad1_hold_force, true)
-    (2,  12, touch_pad2(),     "",      touch_pad2_hold_force, rue,       rde       )
+    (2,  12, touch_pad2(),     "",      touch_pad2_hold_force, true)
-    (15, 13, touch_pad3(),     "",      touch_pad3_hold_force, rue,       rde       )
+    (15, 13, touch_pad3(),     "",      touch_pad3_hold_force, true)
-    (13, 14, touch_pad4(),     "",      touch_pad4_hold_force, rue,       rde       )
+    (13, 14, touch_pad4(),     "",      touch_pad4_hold_force, true)
-    (12, 15, touch_pad5(),     "",      touch_pad5_hold_force, rue,       rde       )
+    (12, 15, touch_pad5(),     "",      touch_pad5_hold_force, true)
-    (14, 16, touch_pad6(),     "",      touch_pad6_hold_force, rue,       rde       )
+    (14, 16, touch_pad6(),     "",      touch_pad6_hold_force, true)
-    (27, 17, touch_pad7(),     "",      touch_pad7_hold_force, rue,       rde       )
+    (27, 17, touch_pad7(),     "",      touch_pad7_hold_force, true)
 }
 
 crate::gpio::touch! {
@@ -860,38 +849,23 @@ crate::gpio::touch! {
     (9, 32, 9, sar_touch_out5, touch_meas_out9, sar_touch_thres5, touch_out_th9, false)
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+#[derive(Clone, Copy)]
-    fn pro_cpu_interrupt_status_read() -> u32 {
+pub(crate) enum InterruptStatusRegisterAccess {
-        unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
+    Bank0,
-    }
+    Bank1,
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
-
-    fn app_cpu_interrupt_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.acpu_int().read().bits()
-    }
-
-    fn app_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.acpu_nmi_int().read().bits()
-    }
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
+impl InterruptStatusRegisterAccess {
-    fn pro_cpu_interrupt_status_read() -> u32 {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_int1().read().bits()
+        match self {
-    }
+            Self::Bank0 => match crate::get_core() {
-
+                crate::Cpu::ProCpu => unsafe { &*GPIO::PTR }.pcpu_int().read().bits(),
-    fn pro_cpu_nmi_status_read() -> u32 {
+                crate::Cpu::AppCpu => unsafe { &*GPIO::PTR }.acpu_int().read().bits(),
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int1().read().bits()
+            },
-    }
+            Self::Bank1 => match crate::get_core() {
-
+                crate::Cpu::ProCpu => unsafe { &*GPIO::PTR }.pcpu_int1().read().bits(),
-    fn app_cpu_interrupt_status_read() -> u32 {
+                crate::Cpu::AppCpu => unsafe { &*GPIO::PTR }.acpu_int1().read().bits(),
-        unsafe { &*GPIO::PTR }.acpu_int1().read().bits()
+            },
-    }
+        }
-
-    fn app_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.acpu_nmi_int1().read().bits()
     }
 }

esp-hal/src/soc/esp32c2/gpio.rs

@@ -32,21 +32,11 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-    },
     peripherals::GPIO,
 };
 
@@ -215,12 +205,13 @@ crate::gpio::analog! {
     4
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+#[derive(Clone, Copy)]
-    fn pro_cpu_interrupt_status_read() -> u32 {
+pub(crate) enum InterruptStatusRegisterAccess {
+    Bank0,
+}
+
+impl InterruptStatusRegisterAccess {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
         unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
     }
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
 }

esp-hal/src/soc/esp32c3/gpio.rs

@@ -32,22 +32,12 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
 
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-    },
     peripherals::GPIO,
 };
 
@@ -233,6 +223,7 @@ crate::gpio::gpio! {
     (21, 0, InputOutput () (0 => U0TXD))
 }
 
+// RTC pins 0 through 5 (inclusive) support GPIO wakeup
 crate::gpio::rtc_pins! {
     0
     1
@@ -251,14 +242,13 @@ crate::gpio::analog! {
     5
 }
 
-// RTC pins 0 through 5 (inclusive) support GPIO wakeup
+#[derive(Clone, Copy)]
+pub(crate) enum InterruptStatusRegisterAccess {
+    Bank0,
+}
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+impl InterruptStatusRegisterAccess {
-    fn pro_cpu_interrupt_status_read() -> u32 {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
         unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
     }
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
 }

esp-hal/src/soc/esp32c6/gpio.rs

@@ -32,22 +32,12 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
 
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-    },
     peripherals::GPIO,
 };
 
@@ -350,12 +340,13 @@ crate::gpio::lp_io::lp_gpio! {
     7
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+#[derive(Clone, Copy)]
-    fn pro_cpu_interrupt_status_read() -> u32 {
+pub(crate) enum InterruptStatusRegisterAccess {
+    Bank0,
+}
+
+impl InterruptStatusRegisterAccess {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
         unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
     }
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
 }

esp-hal/src/soc/esp32h2/gpio.rs

@@ -32,22 +32,12 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
 
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-    },
     peripherals::GPIO,
 };
 
@@ -298,12 +288,13 @@ crate::gpio::analog! {
     5
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+#[derive(Clone, Copy)]
-    fn pro_cpu_interrupt_status_read() -> u32 {
+pub(crate) enum InterruptStatusRegisterAccess {
+    Bank0,
+}
+
+impl InterruptStatusRegisterAccess {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
         unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
     }
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
 }

esp-hal/src/soc/esp32s2/gpio.rs

@@ -43,11 +43,6 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
@@ -55,13 +50,7 @@
 use core::mem::transmute;
 
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-        InterruptStatusRegisterAccessBank1,
-    },
     peripherals::{io_mux, GPIO, IO_MUX},
 };
 
@@ -373,72 +362,67 @@ crate::gpio::gpio! {
 }
 
 crate::gpio::analog! {
-    ( 0,  0,  touch_pad(0),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 0,  0,  touch_pad(0),    "",      true)
-    ( 1,  1,  touch_pad(1),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 1,  1,  touch_pad(1),    "",      true)
-    ( 2,  2,  touch_pad(2),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 2,  2,  touch_pad(2),    "",      true)
-    ( 3,  3,  touch_pad(3),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 3,  3,  touch_pad(3),    "",      true)
-    ( 4,  4,  touch_pad(4),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 4,  4,  touch_pad(4),    "",      true)
-    ( 5,  5,  touch_pad(5),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 5,  5,  touch_pad(5),    "",      true)
-    ( 6,  6,  touch_pad(6),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 6,  6,  touch_pad(6),    "",      true)
-    ( 7,  7,  touch_pad(7),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 7,  7,  touch_pad(7),    "",      true)
-    ( 8,  8,  touch_pad(8),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 8,  8,  touch_pad(8),    "",      true)
-    ( 9,  9,  touch_pad(9),    mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    ( 9,  9,  touch_pad(9),    "",      true)
-    (10, 10,  touch_pad(10),   mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (10, 10,  touch_pad(10),   "",      true)
-    (11, 11,  touch_pad(11),   mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (11, 11,  touch_pad(11),   "",      true)
-    (12, 12,  touch_pad(12),   mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (12, 12,  touch_pad(12),   "",      true)
-    (13, 13,  touch_pad(13),   mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (13, 13,  touch_pad(13),   "",      true)
-    (14, 14,  touch_pad(14),   mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (14, 14,  touch_pad(14),   "",      true)
-    (15, 15,  xtal_32p_pad(),  x32p_mux_sel,  x32p_fun_sel,  x32p_fun_ie,  x32p_rue,  x32p_rde)
+    (15, 15,  xtal_32p_pad(),  "x32p_", true)
-    (16, 16,  xtal_32n_pad(),  x32n_mux_sel,  x32n_fun_sel,  x32n_fun_ie,  x32n_rue,  x32n_rde)
+    (16, 16,  xtal_32n_pad(),  "x32n_", true)
-    (17, 17,  pad_dac1(),      mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (17, 17,  pad_dac1(),      "",      true)
-    (18, 18,  pad_dac2(),      mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (18, 18,  pad_dac2(),      "",      true)
-    (19, 19,  rtc_pad19(),     mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (19, 19,  rtc_pad19(),     "",      true)
-    (20, 20,  rtc_pad20(),     mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (20, 20,  rtc_pad20(),     "",      true)
-    (21, 21,  rtc_pad21(),     mux_sel,       fun_sel,       fun_ie,       rue,       rde)
+    (21, 21,  rtc_pad21(),     "",      true)
 }
 
 crate::gpio::rtc_pins! {
-    ( 0,  0,  touch_pad(0),   "",     touch_pad0_hold,  rue,       rde)
+    ( 0,  0,  touch_pad(0),   "",     touch_pad0_hold,  true)
-    ( 1,  1,  touch_pad(1),   "",     touch_pad1_hold,  rue,       rde)
+    ( 1,  1,  touch_pad(1),   "",     touch_pad1_hold,  true)
-    ( 2,  2,  touch_pad(2),   "",     touch_pad2_hold,  rue,       rde)
+    ( 2,  2,  touch_pad(2),   "",     touch_pad2_hold,  true)
-    ( 3,  3,  touch_pad(3),   "",     touch_pad3_hold,  rue,       rde)
+    ( 3,  3,  touch_pad(3),   "",     touch_pad3_hold,  true)
-    ( 4,  4,  touch_pad(4),   "",     touch_pad4_hold,  rue,       rde)
+    ( 4,  4,  touch_pad(4),   "",     touch_pad4_hold,  true)
-    ( 5,  5,  touch_pad(5),   "",     touch_pad5_hold,  rue,       rde)
+    ( 5,  5,  touch_pad(5),   "",     touch_pad5_hold,  true)
-    ( 6,  6,  touch_pad(6),   "",     touch_pad6_hold,  rue,       rde)
+    ( 6,  6,  touch_pad(6),   "",     touch_pad6_hold,  true)
-    ( 7,  7,  touch_pad(7),   "",     touch_pad7_hold,  rue,       rde)
+    ( 7,  7,  touch_pad(7),   "",     touch_pad7_hold,  true)
-    ( 8,  8,  touch_pad(8),   "",     touch_pad8_hold,  rue,       rde)
+    ( 8,  8,  touch_pad(8),   "",     touch_pad8_hold,  true)
-    ( 9,  9,  touch_pad(9),   "",     touch_pad9_hold,  rue,       rde)
+    ( 9,  9,  touch_pad(9),   "",     touch_pad9_hold,  true)
-    (10, 10,  touch_pad(10),  "",     touch_pad10_hold, rue,       rde)
+    (10, 10,  touch_pad(10),  "",     touch_pad10_hold, true)
-    (11, 11,  touch_pad(11),  "",     touch_pad11_hold, rue,       rde)
+    (11, 11,  touch_pad(11),  "",     touch_pad11_hold, true)
-    (12, 12,  touch_pad(12),  "",     touch_pad12_hold, rue,       rde)
+    (12, 12,  touch_pad(12),  "",     touch_pad12_hold, true)
-    (13, 13,  touch_pad(13),  "",     touch_pad13_hold, rue,       rde)
+    (13, 13,  touch_pad(13),  "",     touch_pad13_hold, true)
-    (14, 14,  touch_pad(14),  "",     touch_pad14_hold, rue,       rde)
+    (14, 14,  touch_pad(14),  "",     touch_pad14_hold, true)
-    (15, 15,  xtal_32p_pad(), x32p_,  x32p_hold,        x32p_rue,  x32p_rde)
+    (15, 15,  xtal_32p_pad(), x32p_,  x32p_hold,        true)
-    (16, 16,  xtal_32n_pad(), x32n_,  x32n_hold,        x32n_rue,  x32n_rde)
+    (16, 16,  xtal_32n_pad(), x32n_,  x32n_hold,        true)
-    (17, 17,  pad_dac1(),     "",     pdac1_hold,       rue,       rde)
+    (17, 17,  pad_dac1(),     "",     pdac1_hold,       true)
-    (18, 18,  pad_dac2(),     "",     pdac2_hold,       rue,       rde)
+    (18, 18,  pad_dac2(),     "",     pdac2_hold,       true)
-    (19, 19,  rtc_pad19(),    "",     pad19_hold,       rue,       rde)
+    (19, 19,  rtc_pad19(),    "",     pad19_hold,       true)
-    (20, 20,  rtc_pad20(),    "",     pad20_hold,       rue,       rde)
+    (20, 20,  rtc_pad20(),    "",     pad20_hold,       true)
-    (21, 21,  rtc_pad21(),    "",     pad21_hold,       rue,       rde)
+    (21, 21,  rtc_pad21(),    "",     pad21_hold,       true)
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+#[derive(Clone, Copy)]
-    fn pro_cpu_interrupt_status_read() -> u32 {
+pub(crate) enum InterruptStatusRegisterAccess {
-        unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
+    Bank0,
-    }
+    Bank1,
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
+impl InterruptStatusRegisterAccess {
-    fn pro_cpu_interrupt_status_read() -> u32 {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_int1().read().bits()
+        match self {
-    }
+            Self::Bank0 => unsafe { &*GPIO::PTR }.pcpu_int().read().bits(),
-
+            Self::Bank1 => unsafe { &*GPIO::PTR }.pcpu_int1().read().bits(),
-    fn pro_cpu_nmi_status_read() -> u32 {
+        }
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int1().read().bits()
     }
 }
 

esp-hal/src/soc/esp32s3/gpio.rs

@@ -32,23 +32,12 @@
 //!       * This enumeration defines output signals for the GPIO mux. Each
 //!         output signal is assigned a specific value.
 //!
-//! This module also implements the `InterruptStatusRegisterAccess` trait for
-//! two different banks:
-//!   * `InterruptStatusRegisterAccessBank0`
-//!   * `InterruptStatusRegisterAccessBank1`.
-//!
 //! This trait provides functions to read the interrupt status and NMI status
 //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
 //! `gpio` peripheral to access the appropriate registers.
 
 use crate::{
-    gpio::{
+    gpio::{AlternateFunction, GpioPin},
-        AlternateFunction,
-        GpioPin,
-        InterruptStatusRegisterAccess,
-        InterruptStatusRegisterAccessBank0,
-        InterruptStatusRegisterAccessBank1,
-    },
     peripherals::GPIO,
 };
 
@@ -405,90 +394,69 @@ crate::gpio::gpio! {
 }
 
 crate::gpio::analog! {
-    ( 0,  0,  touch_pad(0),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 0,  0,  touch_pad(0),     "",       true)
-    ( 1,  1,  touch_pad(1),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 1,  1,  touch_pad(1),     "",       true)
-    ( 2,  2,  touch_pad(2),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 2,  2,  touch_pad(2),     "",       true)
-    ( 3,  3,  touch_pad(3),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 3,  3,  touch_pad(3),     "",       true)
-    ( 4,  4,  touch_pad(4),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 4,  4,  touch_pad(4),     "",       true)
-    ( 5,  5,  touch_pad(5),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 5,  5,  touch_pad(5),     "",       true)
-    ( 6,  6,  touch_pad(6),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 6,  6,  touch_pad(6),     "",       true)
-    ( 7,  7,  touch_pad(7),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 7,  7,  touch_pad(7),     "",       true)
-    ( 8,  8,  touch_pad(8),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 8,  8,  touch_pad(8),     "",       true)
-    ( 9,  9,  touch_pad(9),     mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    ( 9,  9,  touch_pad(9),     "",       true)
-    (10, 10,  touch_pad(10),    mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (10, 10,  touch_pad(10),    "",       true)
-    (11, 11,  touch_pad(11),    mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (11, 11,  touch_pad(11),    "",       true)
-    (12, 12,  touch_pad(12),    mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (12, 12,  touch_pad(12),    "",       true)
-    (13, 13,  touch_pad(13),    mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (13, 13,  touch_pad(13),    "",       true)
-    (14, 14,  touch_pad(14),    mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (14, 14,  touch_pad(14),    "",       true)
-    (15, 15,  xtal_32p_pad(),   x32p_mux_sel, x32p_fun_sel, x32p_fun_ie,    x32p_rue,  x32p_rde)
+    (15, 15,  xtal_32p_pad(),   "x32p_",  true)
-    (16, 16,  xtal_32n_pad(),   x32n_mux_sel, x32n_fun_sel, x32n_fun_ie,    x32n_rue,  x32n_rde)
+    (16, 16,  xtal_32n_pad(),   "x32n_",  true)
-    (17, 17,  pad_dac1(),       pdac1_mux_sel,pdac1_fun_sel,pdac1_fun_ie,  pdac1_rue, pdac1_rde)
+    (17, 17,  pad_dac1(),       "pdac1_", true)
-    (18, 18,  pad_dac2(),       pdac2_mux_sel,pdac2_fun_sel,pdac2_fun_ie,  pdac2_rue, pdac2_rde)
+    (18, 18,  pad_dac2(),       "pdac2_", true)
-    (19, 19,  rtc_pad19(),      mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (19, 19,  rtc_pad19(),      "",       true)
-    (20, 20,  rtc_pad20(),      mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (20, 20,  rtc_pad20(),      "",       true)
-    (21, 21,  rtc_pad21(),      mux_sel,      fun_sel,      fun_ie,              rue,       rde)
+    (21, 21,  rtc_pad21(),      "",       true)
 }
 
 crate::gpio::rtc_pins! {
-    ( 0,  0,  touch_pad(0),   "",     touch_pad0_hold,        rue,       rde)
+    ( 0,  0,  touch_pad(0),   "",     touch_pad0_hold,  true)
-    ( 1,  1,  touch_pad(1),   "",     touch_pad1_hold,        rue,       rde)
+    ( 1,  1,  touch_pad(1),   "",     touch_pad1_hold,  true)
-    ( 2,  2,  touch_pad(2),   "",     touch_pad2_hold,        rue,       rde)
+    ( 2,  2,  touch_pad(2),   "",     touch_pad2_hold,  true)
-    ( 3,  3,  touch_pad(3),   "",     touch_pad3_hold,        rue,       rde)
+    ( 3,  3,  touch_pad(3),   "",     touch_pad3_hold,  true)
-    ( 4,  4,  touch_pad(4),   "",     touch_pad4_hold,        rue,       rde)
+    ( 4,  4,  touch_pad(4),   "",     touch_pad4_hold,  true)
-    ( 5,  5,  touch_pad(5),   "",     touch_pad5_hold,        rue,       rde)
+    ( 5,  5,  touch_pad(5),   "",     touch_pad5_hold,  true)
-    ( 6,  6,  touch_pad(6),   "",     touch_pad6_hold,        rue,       rde)
+    ( 6,  6,  touch_pad(6),   "",     touch_pad6_hold,  true)
-    ( 7,  7,  touch_pad(7),   "",     touch_pad7_hold,        rue,       rde)
+    ( 7,  7,  touch_pad(7),   "",     touch_pad7_hold,  true)
-    ( 8,  8,  touch_pad(8),   "",     touch_pad8_hold,        rue,       rde)
+    ( 8,  8,  touch_pad(8),   "",     touch_pad8_hold,  true)
-    ( 9,  9,  touch_pad(9),   "",     touch_pad9_hold,        rue,       rde)
+    ( 9,  9,  touch_pad(9),   "",     touch_pad9_hold,  true)
-    (10, 10,  touch_pad(10),  "",     touch_pad10_hold,       rue,       rde)
+    (10, 10,  touch_pad(10),  "",     touch_pad10_hold, true)
-    (11, 11,  touch_pad(11),  "",     touch_pad11_hold,       rue,       rde)
+    (11, 11,  touch_pad(11),  "",     touch_pad11_hold, true)
-    (12, 12,  touch_pad(12),  "",     touch_pad12_hold,       rue,       rde)
+    (12, 12,  touch_pad(12),  "",     touch_pad12_hold, true)
-    (13, 13,  touch_pad(13),  "",     touch_pad13_hold,       rue,       rde)
+    (13, 13,  touch_pad(13),  "",     touch_pad13_hold, true)
-    (14, 14,  touch_pad(14),  "",     touch_pad14_hold,       rue,       rde)
+    (14, 14,  touch_pad(14),  "",     touch_pad14_hold, true)
-    (15, 15,  xtal_32p_pad(), x32p_,  x32p_hold,         x32p_rue,  x32p_rde)
+    (15, 15,  xtal_32p_pad(), x32p_,  x32p_hold,        true)
-    (16, 16,  xtal_32n_pad(), x32n_,  x32n_hold,         x32n_rue,  x32n_rde)
+    (16, 16,  xtal_32n_pad(), x32n_,  x32n_hold,        true)
-    (17, 17,  pad_dac1(),     pdac1_, pdac1_hold,       pdac1_rue, pdac1_rde)
+    (17, 17,  pad_dac1(),     pdac1_, pdac1_hold,       true)
-    (18, 18,  pad_dac2(),     pdac2_, pdac2_hold,       pdac2_rue, pdac2_rde)
+    (18, 18,  pad_dac2(),     pdac2_, pdac2_hold,       true)
-    (19, 19,  rtc_pad19(),    "",     pad19_hold,             rue,       rde)
+    (19, 19,  rtc_pad19(),    "",     pad19_hold,       true)
-    (20, 20,  rtc_pad20(),    "",     pad20_hold,             rue,       rde)
+    (20, 20,  rtc_pad20(),    "",     pad20_hold,       true)
-    (21, 21,  rtc_pad21(),    "",     pad21_hold,             rue,       rde)
+    (21, 21,  rtc_pad21(),    "",     pad21_hold,       true)
 }
 
 // Whilst the S3 is a dual core chip, it shares the enable registers between
 // cores so treat it as a single core device
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
+#[derive(Clone, Copy)]
-    fn pro_cpu_interrupt_status_read() -> u32 {
+pub(crate) enum InterruptStatusRegisterAccess {
-        unsafe { &*GPIO::PTR }.pcpu_int().read().bits()
+    Bank0,
-    }
+    Bank1,
-
-    fn pro_cpu_nmi_status_read() -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
-    }
-
-    fn interrupt_status_read() -> u32 {
-        Self::pro_cpu_interrupt_status_read()
-    }
-
-    fn nmi_status_read() -> u32 {
-        Self::pro_cpu_nmi_status_read()
-    }
 }
 
-impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
+impl InterruptStatusRegisterAccess {
-    fn pro_cpu_interrupt_status_read() -> u32 {
+    pub(crate) fn interrupt_status_read(self) -> u32 {
-        unsafe { &*GPIO::PTR }.pcpu_int1().read().bits()
+        match self {
-    }
+            Self::Bank0 => unsafe { &*GPIO::PTR }.pcpu_int().read().bits(),
-
+            Self::Bank1 => unsafe { &*GPIO::PTR }.pcpu_int1().read().bits(),
-    fn pro_cpu_nmi_status_read() -> u32 {
+        }
-        unsafe { &*GPIO::PTR }.pcpu_nmi_int1().read().bits()
-    }
-
-    fn interrupt_status_read() -> u32 {
-        Self::pro_cpu_interrupt_status_read()
-    }
-
-    fn nmi_status_read() -> u32 {
-        Self::pro_cpu_nmi_status_read()
     }
 }